diff options
| author | John Zhao <john.zhao@intel.com> | 2019-01-10 11:09:09 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:00:19 +0000 |
| commit | 8cf6d4d7d68e13577b498a0518d2511e5fff0f59 (patch) | |
| tree | 8be6fce89775d3ce858b5a3de7129805a515f909 /src/northbridge/intel | |
| parent | 2fbb6773e3a6d5d18e84b0ac79b645147fbf0d66 (diff) | |
mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE masked
PLT_RST_L was asserted twice at boot-up and a glitch was observed
when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE
from HIZCRx1 to be masked.
BRANCH=octopus
BUG=b:117302959
TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high
3.3v during S0ix.
Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30815
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions