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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 12:00:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:11:01 +0000 |
| commit | 7adc370dc79af1aacd6f811b9b28d01d595da702 (patch) | |
| tree | cfbd1e26139cfd9e40884cb8b1af1ca507893603 /src/northbridge/intel | |
| parent | a28ee1b186b098ef6ce9b97b094d500bef4b1a94 (diff) | |
intel/{i945,pineview},i82801gx: Move enable_smbus() call
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/romstage.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 2 |
2 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 479588129d..ff4ccc195e 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -61,9 +61,6 @@ void mainboard_romstage_entry(void) s3resume = southbridge_detect_s3_resume(); - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - mainboard_pre_raminit_config(s3resume); if (CONFIG(DEBUG_RAM_SETUP)) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e324c05327..ce4cd5531b 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -51,8 +51,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - enable_smbus(); - /* Perform some early chipset initialization required * before RAM initialization can work */ |