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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-08 01:53:24 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-11 08:39:07 +0200
commit7116ac803736345cc7c7b73ac435efa50c4cd2b0 (patch)
tree64b7190ef4e61ba2e17a88c50e92c076c3aa2d19 /src/northbridge/intel
parentc805e62f9dd5e1b11906101845abd36b049e7dc3 (diff)
src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/gm45/raminit.c2
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c10
-rw-r--r--src/northbridge/intel/nehalem/raminit.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 0636d9f9f2..1f667609f4 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -362,7 +362,7 @@ static void collect_ddr3(spdinfo_t *const config)
}
}
-#define ROUNDUP_DIV(val, by) (((val) + (by) - 1) / (by))
+#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by)
#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by)
static fsb_clock_t read_fsb_clock(void)
{
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 90c1005b4c..962b7aa86b 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -335,7 +335,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH);
val <<= 2; /* convert to 1/4 ns */
val += byte40rem[(val1 >> 4) & 0x7];
- val = (val + ci - 1) / ci + 1; /* convert to cycles */
+ val = CEIL_DIV(val, ci) + 1; /* convert to cycles */
if (trc < val)
trc = val;
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT);
@@ -343,7 +343,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (val1 & 0x01)
val += 1024;
val += byte40rem[(val1 >> 1) & 0x7];
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (trfc < val)
trfc = val;
}
@@ -360,15 +360,15 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
continue;
val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
val <<= 2; /* convert to 1/4 ns */
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (tras < val)
tras = val;
val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY);
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (trtp < val)
trtp = val;
val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY);
- val = (val + ci - 1) / ci; /* convert to cycles */
+ val = CEIL_DIV(val, ci); /* convert to cycles */
if (twtr < val)
twtr = val;
}
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 761dc527bf..6673b5a846 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -647,7 +647,7 @@ static void calculate_timings(struct raminfo *info)
break;
}
}
- min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime;
+ min_cas_latency = CEIL_DIV(cas_latency_time, cycletime);
cas_latency = 0;
while (supported_cas_latencies) {
cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
@@ -3337,7 +3337,7 @@ static unsigned gcd(unsigned a, unsigned b)
static inline int div_roundup(int a, int b)
{
- return (a + b - 1) / b;
+ return CEIL_DIV(a, b);
}
static unsigned lcm(unsigned a, unsigned b)