diff options
| author | Martin Roth <martin@coreboot.org> | 2020-07-24 12:24:27 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:20:30 +0000 |
| commit | f48acbda7be7074938c06db8ad37705f850661ee (patch) | |
| tree | 4e06af0923d793db47700aae5a5b3f374c8529d8 /src/northbridge/intel | |
| parent | af56a7791565de4c3dec66b4cc6a8b152bba014c (diff) | |
src: Change BOOL CONFIG_ to CONFIG() in comments & strings
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/bootblock.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/bootblock.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/bootblock.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e74354ebdb..a0e8fc0631 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be337..59c31aa672 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent * non-explicit config accesses use MCFG. This code also assumes that * bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 9d06120ecb..60051babd3 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -10,10 +10,10 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final assumption is that - * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 37ef02531e..dad61f9ee8 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all + * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ |