summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-10-10 15:06:33 +0200
committerNico Huber <nico.h@gmx.de>2019-10-13 11:07:00 +0000
commitb9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (patch)
treeb5b3a4327f21a40011605347c2a3694bac6e6efa /src/northbridge/intel
parentb33d8ce5c7cb71117a7a65a0775c5a16c7bc4517 (diff)
sb/intel/ibexpeak: Move some early PCH init after console init
Some of the initialization isn't necessary before console INIT is done. EHCI debug still works fine on the Lenovo Thinkpad X201. Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/nehalem/romstage.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c
index c465a99365..54766de0e7 100644
--- a/src/northbridge/intel/nehalem/romstage.c
+++ b/src/northbridge/intel/nehalem/romstage.c
@@ -45,11 +45,13 @@ void mainboard_romstage_entry(void)
/* TODO, make this configurable */
nehalem_early_initialization(NEHALEM_MOBILE);
- early_pch_init();
+ pch_pre_console_init();
/* Initialize console device(s) */
console_init();
+ early_pch_init();
+
/* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);