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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-09 11:59:00 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-14 09:32:34 +0000
commitb0f1988f893bf5f581917816b11e810309955143 (patch)
treec4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/northbridge/intel
parent68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff)
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7505/e7505.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
index 5ceeacceaf..b80d8a8a52 100644
--- a/src/northbridge/intel/e7505/e7505.h
+++ b/src/northbridge/intel/e7505/e7505.h
@@ -26,7 +26,7 @@
#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
-#define PAM_0 0x59
+#define PAM_0 0x59
#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
#define DRB_ROW_1 0x61