diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2022-01-26 07:51:28 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 14:48:35 +0000 |
| commit | a233eb4b0a92c56e2d91a533b96bafbdf0413c9c (patch) | |
| tree | 19c324283ae5e8298099561895459a88b2e5fd0c /src/northbridge/intel | |
| parent | 62b23c10e03fb713bdd9caf888c52c89ee79fb66 (diff) | |
nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 0a7d1921d8..4027708617 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -14,6 +14,7 @@ #include <device/pci_def.h> #include <lib.h> #include <mrc_cache.h> +#include <spd.h> #include <smbios.h> #include <stddef.h> #include <stdint.h> @@ -429,7 +430,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][118] << 8) | (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } @@ -453,7 +454,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][118] << 8) | (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } |