haswell: remove explicit pcie config accesses

Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2 files changed, 12 insertions, 102 deletions

diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 01843c9fee..58052f9952 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -21,24 +21,23 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <stdlib.h>
-#include "pcie_config.c"
 #include "haswell.h"
 
-#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
+#define PCI_DEV_HSW PCI_DEV(0, 0, 0)
 
 void intel_northbridge_haswell_finalize_smm(void)
 {
-	pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);	/* GGC */
-	pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);	/* DPR */
-	pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);	/* ME */
-	pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);	/* REMAPBASE */
-	pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);	/* REMAPLIMIT */
-	pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);	/* TOM */
-	pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);	/* TOUUD */
-	pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);	/* BDSM */
-	pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0);	/* BGSM */
-	pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0);	/* TSEGMB */
-	pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0);	/* TOLUD */
+	pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0);	/* GGC */
+	pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0);	/* DPR */
+	pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10);	/* ME */
+	pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0);	/* REMAPBASE */
+	pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0);	/* REMAPLIMIT */
+	pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0);	/* TOM */
+	pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0);	/* TOUUD */
+	pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0);	/* BDSM */
+	pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0);	/* BGSM */
+	pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0);	/* TSEGMB */
+	pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0);	/* TOLUD */
 
 	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
 	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
diff --git a/src/northbridge/intel/haswell/pcie_config.c b/src/northbridge/intel/haswell/pcie_config.c
deleted file mode 100644
index d96854e739..0000000000
--- a/src/northbridge/intel/haswell/pcie_config.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "haswell.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
-{
-	u8 value = pcie_read_config8(dev, where);
-	pcie_write_config8(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
-{
-	u16 value = pcie_read_config16(dev, where);
-	pcie_write_config16(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
-{
-	u32 value = pcie_read_config32(dev, where);
-	pcie_write_config32(dev, where, value | ormask);
-}