diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-03 09:44:28 +0300 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 00:57:09 +0200 |
| commit | 872c9222965909dffdd091e644b03e676ca2754f (patch) | |
| tree | 25de10840a1ff5d3078f89949a72c767693ee8c1 /src/northbridge/intel | |
| parent | 20b6d91fd33f5d90d1c51e2fb813453349398b73 (diff) | |
Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.
The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.
Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sch/northbridge.c | 6 |
6 files changed, 6 insertions, 30 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 3a4439cc55..687479e807 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -202,11 +202,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 45d967e788..9f027343e4 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -98,11 +98,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 113dc56359..01f150e82b 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -168,11 +168,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static void enable_dev(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c17a..7e21164276 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -185,11 +185,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static void mc_read_resources(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index d8e2e9d6b3..e3290d8985 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -289,11 +289,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static void mc_read_resources(device_t dev) diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 06d34d834b..600bd13cd4 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -200,11 +200,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static void mc_read_resources(device_t dev) |