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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-30 20:23:09 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-15 03:52:49 +0000 |
| commit | 86091f94b6ca58f4b8795503b274492d6a935c15 (patch) | |
| tree | db6e5f77dc57850b25574aed5063743ca4bc4d48 /src/northbridge/intel | |
| parent | 58562405c8c416a415652516b8af31b204b4ff0d (diff) | |
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 12 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index fc715bc1de..b48328f1b7 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -986,10 +986,10 @@ static inline void __attribute__((always_inline)) */ /* Disable and invalidate all cache. */ - msr_t xip_mtrr = rdmsr(MTRRphysMask_MSR(1)); - xip_mtrr.lo &= ~MTRRphysMaskValid; + msr_t xip_mtrr = rdmsr(MTRR_PHYS_MASK(1)); + xip_mtrr.lo &= ~MTRR_PHYS_MASK_VALID; invd(); - wrmsr(MTRRphysMask_MSR(1), xip_mtrr); + wrmsr(MTRR_PHYS_MASK(1), xip_mtrr); invd(); RAM_DEBUG_MESSAGE("ECC state initialized.\n"); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c41310a69a..232a15a239 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -2066,8 +2066,8 @@ static void disable_cache(void) { msr_t msr = {.lo = 0, .hi = 0 }; - wrmsr(MTRRphysBase_MSR(3), msr); - wrmsr(MTRRphysMask_MSR(3), msr); + wrmsr(MTRR_PHYS_BASE(3), msr); + wrmsr(MTRR_PHYS_MASK(3), msr); } static void enable_cache(unsigned int base, unsigned int size) @@ -2075,11 +2075,11 @@ static void enable_cache(unsigned int base, unsigned int size) msr_t msr; msr.lo = base | MTRR_TYPE_WRPROT; msr.hi = 0; - wrmsr(MTRRphysBase_MSR(3), msr); - msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn) + wrmsr(MTRR_PHYS_BASE(3), msr); + msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN) & 0xffffffff); msr.hi = 0x0000000f; - wrmsr(MTRRphysMask_MSR(3), msr); + wrmsr(MTRR_PHYS_MASK(3), msr); } static void flush_cache(u32 start, u32 size) @@ -4017,7 +4017,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc); #if !REAL - rdmsr (MTRRphysMask_MSR (3)); + rdmsr (MTRR_PHYS_MASK (3)); #endif collect_system_info(&info); |