src/northbridge: Remove unnecessary whitespace

Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

9 files changed, 36 insertions, 36 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c
index 60a3e00e4f..39bbc09510 100644
--- a/src/northbridge/intel/fsp_sandybridge/report_platform.c
+++ b/src/northbridge/intel/fsp_sandybridge/report_platform.c
@@ -41,7 +41,7 @@ static void report_cpu_info(void)
 		strcpy(cpu_string, "Platform info not available");
 	} else {
 		u32 *p = (u32*) cpu_string;
-		for (i = 2; i <= 4 ; i++) {
+		for (i = 2; i <= 4; i++) {
 			cpuidr = cpuid(index + i);
 			*p++ = cpuidr.eax;
 			*p++ = cpuidr.ebx;
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 3f56b94945..47203b4186 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -49,12 +49,12 @@ static void init_egress(void)
 	EPBAR32(0x11c) = 0x00005555;
 	EPBAR32(0x20) |= 1 << 16;
 
-	while ((EPBAR8(0x26) & 1) != 0) ;
+	while ((EPBAR8(0x26) & 1) != 0);
 
 	/* VC1: enable */
 	EPBAR32(0x20) |= 1 << 31;
 
-	while ((EPBAR8(0x26) & 2) != 0) ;
+	while ((EPBAR8(0x26) & 2) != 0);
 }
 
 /* MCH side */
@@ -72,7 +72,7 @@ static void init_dmi(int b2step)
 	/* VC1: enable */
 	DMIBAR32(0x20) |= 1 << 31;
 
-	while ((DMIBAR8(0x26) & 2) != 0) ;
+	while ((DMIBAR8(0x26) & 2) != 0);
 
 	/* additional configuration. */
 	DMIBAR32(0x200) |= 3 << 13;
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 711ff48d69..aed125c8bc 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -36,7 +36,7 @@ static void report_cpu_info(void)
 		strcpy(cpu_string, "Platform info not available");
 	} else {
 		u32 *p = (u32*) cpu_string;
-		for (i = 2; i <= 4 ; i++) {
+		for (i = 2; i <= 4; i++) {
 			cpuidr = cpuid(index + i);
 			*p++ = cpuidr.eax;
 			*p++ = cpuidr.ebx;
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index fa00df8eea..4804544555 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -85,7 +85,7 @@ void dump_spd_registers(void)
 		int i;
 		printk(BIOS_DEBUG, "\ndimm %02x", device);
 
-		for (i = 0; (i < 256) ; i++) {
+		for (i = 0; (i < 256); i++) {
 			if ((i % 16) == 0) {
 				printk(BIOS_DEBUG, "\n%02x: ", i);
 			}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index dda41bd6d7..4373167693 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -285,7 +285,7 @@ static void i945_setup_egress_port(void)
 	printk(BIOS_DEBUG, "Loading port arbitration table ...");
 	/* Loop until bit 0 becomes 0 */
 	timeout = 0x7fffff;
-	while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
+	while ((EPBAR16(EPVC1RSTS) & 1) && --timeout);
 	if (!timeout)
 		printk(BIOS_DEBUG, "timeout!\n");
 	else
@@ -297,7 +297,7 @@ static void i945_setup_egress_port(void)
 	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7fff;
-	while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
+	while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout);
 	if (!timeout)
 		printk(BIOS_DEBUG, "timeout!\n");
 	else
@@ -390,7 +390,7 @@ static void i945_setup_dmi_rcrb(void)
 	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7ffff;
-	while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
+	while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout);
 	if (!timeout)
 		printk(BIOS_DEBUG, "timeout!\n");
 	else
@@ -490,7 +490,7 @@ static void i945_setup_dmi_rcrb(void)
 	/* wait for bit toggle to 0 */
 	printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 	timeout = 0x7fffff;
-	while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
+	while ((DMIBAR8(0x32) & (1 << 1)) && --timeout);
 	if (!timeout)
 		printk(BIOS_DEBUG, "timeout!\n");
 	else
@@ -593,7 +593,7 @@ static void i945_setup_pci_express_x16(void)
 	/* Wait for training to succeed */
 	printk(BIOS_DEBUG, "PCIe link training ...");
 	timeout = 0x7ffff;
-	while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout) ;
+	while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout);
 
 	reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
 	if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -618,7 +618,7 @@ static void i945_setup_pci_express_x16(void)
 
 		printk(BIOS_DEBUG, "PCIe link training ...");
 		timeout = 0x7ffff;
-		while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout) ;
+		while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout);
 
 		reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
 		if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -793,7 +793,7 @@ disable_pciexpress_x16_link:
 	printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 	timeout = 0x7fffff;
 	for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
-	     (reg32 & 0x000f0000) && --timeout;) ;
+	     (reg32 & 0x000f0000) && --timeout;);
 	if (!timeout)
 		printk(BIOS_DEBUG, "timeout!\n");
 	else
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 69e7108271..d9159966dc 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -173,12 +173,12 @@ static void read128(u32 addr, u64 * out)
 static void write_1d0(u32 val, u16 addr, int bits, int flag)
 {
 	write_mchbar32(0x1d0, 0);
-	while (read_mchbar32(0x1d0) & 0x800000) ;
+	while (read_mchbar32(0x1d0) & 0x800000);
 	write_mchbar32(0x1d4,
 		       (val & ((1 << bits) - 1)) | (2 << bits) | (flag <<
 								  bits));
 	write_mchbar32(0x1d0, 0x40000000 | addr);
-	while (read_mchbar32(0x1d0) & 0x800000) ;
+	while (read_mchbar32(0x1d0) & 0x800000);
 }
 
 /* OK */
@@ -186,11 +186,11 @@ static u16 read_1d0(u16 addr, int split)
 {
 	u32 val;
 	write_mchbar32(0x1d0, 0);
-	while (read_mchbar32(0x1d0) & 0x800000) ;
+	while (read_mchbar32(0x1d0) & 0x800000);
 	write_mchbar32(0x1d0,
 		       0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) +
 				     0x361 - addr));
-	while (read_mchbar32(0x1d0) & 0x800000) ;
+	while (read_mchbar32(0x1d0) & 0x800000);
 	val = read_mchbar32(0x1d8);
 	write_1d0(0, 0x33d, 0, 0);
 	write_1d0(0, 0x33d, 0, 0);
@@ -289,12 +289,12 @@ read_500(struct raminfo *info, int channel, u16 addr, int split)
 	u32 val;
 	info->last_500_command[channel] = 0x80000000;
 	write_mchbar32(0x500 + (channel << 10), 0);
-	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000);
 	write_mchbar32(0x500 + (channel << 10),
 		       0x80000000 |
 		       (((read_mchbar8(0x246 + (channel << 10)) >> 2) &
 			 3) + 0xb88 - addr));
-	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000);
 	val = read_mchbar32(0x508 + (channel << 10));
 	return val & ((1 << split) - 1);
 }
@@ -309,12 +309,12 @@ write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
 		write_500(info, channel, 0, 0xb61, 0, 0);
 	}
 	write_mchbar32(0x500 + (channel << 10), 0);
-	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000);
 	write_mchbar32(0x504 + (channel << 10),
 		       (val & ((1 << bits) - 1)) | (2 << bits) | (flag <<
 								  bits));
 	write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr);
-	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+	while (read_mchbar32(0x500 + (channel << 10)) & 0x800000);
 }
 
 static int rw_test(int rank)
@@ -391,7 +391,7 @@ static u32 get_580(int channel, u8 addr)
 	write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr);
 	write_mchbar8(0x580 + (channel << 10),
 		      read_mchbar8(0x580 + (channel << 10)) | 1);
-	while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ;
+	while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000));
 	write_mchbar8(0x580 + (channel << 10),
 		      read_mchbar8(0x580 + (channel << 10)) & ~1);
 	return ret;
@@ -548,7 +548,7 @@ static void set_334(int zero)
 	}
 
 	write_mchbar32(0x130, read_mchbar32(0x130) | 1);	/* OK */
-	while (read_mchbar8(0x130) & 1) ;	/* OK */
+	while (read_mchbar8(0x130) & 1);	/* OK */
 }
 
 static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag)
@@ -1593,7 +1593,7 @@ static void collect_system_info(struct raminfo *info)
 	unsigned channel;
 
 	/* Wait for some bit, maybe TXT clear. */
-	while (!(read8((u8 *)0xfed40000) & (1 << 7))) ;
+	while (!(read8((u8 *)0xfed40000) & (1 << 7)));
 
 	if (!info->heci_bar)
 		gav(info->heci_bar =
@@ -1756,7 +1756,7 @@ static const struct ram_training *get_cached_training(void)
 /* FIXME: add timeout.  */
 static void wait_heci_ready(void)
 {
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;	// = 0x8000000c
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));	// = 0x8000000c
 	write32((DEFAULT_HECIBAR + 0x4),
 		(read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
 }
@@ -1769,7 +1769,7 @@ static void wait_heci_cb_avail(int len)
 		u32 raw;
 	} csr;
 
-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8));
 
 	do
 		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
@@ -1971,7 +1971,7 @@ static void setup_heci_uma(struct raminfo *info)
 		write32(DEFAULT_RCBA + 0x40, 0x87000080);	// OK
 		write32(DEFAULT_DMIBAR + 0x38, 0x87000080);	// OK
 		while (read16(DEFAULT_RCBA + 0x46) & 2
-		       && read16(DEFAULT_DMIBAR + 0x3e) & 2) ;
+		       && read16(DEFAULT_DMIBAR + 0x3e) & 2);
 	}
 
 	write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -4551,7 +4551,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 	write_mchbar8(0x5f4, 0x1);	/* OK */
 
 	write_mchbar32(0x130, read_mchbar32(0x130) & 0xfffffffd);	// | 2 when ?
-	while (read_mchbar32(0x130) & 1) ;
+	while (read_mchbar32(0x130) & 1);
 	gav(read_1d0(0x14b, 7));	// = 0x81023100
 	write_1d0(0x30, 0x14b, 7, 1);
 	read_1d0(0xd6, 6);	// = 0xfa008080 // !!!!
@@ -4622,7 +4622,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 									[0][0]
 									[0] <<
 									29));
-	while (read_mchbar8(0x130) & 1) ;	// !!!!
+	while (read_mchbar8(0x130) & 1);	// !!!!
 	read_1d0(0xa1, 6);	// = 0x1cf4054 // !!!!
 	read_1d0(0x2f3, 6);	// = 0x10a4054 // !!!!
 	read_1d0(0x21c, 6);	// = 0xafa00c0 // !!!!
@@ -4962,7 +4962,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 		udelay(1000);
 #endif
 		u16 ecx;
-		for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--) ;	// OK
+		for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--);	// OK
 		write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000);	// OK
 	}
 
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 1e46263f93..46dc7c7843 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -225,7 +225,7 @@ static void wait_txt_clear(void)
 	if (!(read32((void *)0xfed30010) & 1))
 		return;
 	/* Wait for TXT clear.  */
-	while (!(read8((void *)0xfed40000) & (1 << 7))) ;
+	while (!(read8((void *)0xfed40000) & (1 << 7)));
 }
 
 static void sfence(void)
@@ -1322,7 +1322,7 @@ static void dram_jedecreset(ramctr_timing * ctrl)
 	u32 reg, addr;
 	int channel;
 
-	while (!(MCHBAR32(0x5084) & 0x10000)) ;
+	while (!(MCHBAR32(0x5084) & 0x10000));
 	do {
 		reg = MCHBAR32(0x428c);
 	} while ((reg & 0x14) == 0);
@@ -3997,7 +3997,7 @@ static void restore_timings(ramctr_timing * ctrl)
 
 	u32 reg, addr;
 
-	while (!(MCHBAR32(0x5084) & 0x10000)) ;
+	while (!(MCHBAR32(0x5084) & 0x10000));
 	do {
 		reg = MCHBAR32(0x428c);
 	} while ((reg & 0x14) == 0);
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
index 39bff65b8b..d137e8b63b 100644
--- a/src/northbridge/intel/sandybridge/report_platform.c
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -34,7 +34,7 @@ static void report_cpu_info(void)
 		strcpy(cpu_string, "Platform info not available");
 	} else {
 		u32 *p = (u32*) cpu_string;
-		for (i = 2; i <= 4 ; i++) {
+		for (i = 2; i <= 4; i++) {
 			cpuidr = cpuid(index + i);
 			*p++ = cpuidr.eax;
 			*p++ = cpuidr.ebx;
diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c
index 7eb67ff071..f03869e346 100644
--- a/src/northbridge/intel/x4x/pcie.c
+++ b/src/northbridge/intel/x4x/pcie.c
@@ -80,13 +80,13 @@ static void init_egress(void)
 	EPBAR32(0x20) = reg32;
 
 	/* Wait for table load */
-	while ((EPBAR8(0x26) & (1 << 0)) != 0) ;
+	while ((EPBAR8(0x26) & (1 << 0)) != 0);
 
 	/* VC1: enable */
 	EPBAR32(0x20) |= 1 << 31;
 
 	/* Wait for VC1 */
-	while ((EPBAR8(0x26) & (1 << 1)) != 0) ;
+	while ((EPBAR8(0x26) & (1 << 1)) != 0);
 
 	printk(BIOS_DEBUG, "Done Egress Port\n");
 }