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authorPatrick Rudolph <siro@das-labor.org>2016-02-28 16:14:45 +0100
committerMartin Roth <martinroth@google.com>2016-03-02 21:38:28 +0100
commit77e45d3eccc5cf82a2b4d4d1cd47654dec1962b4 (patch)
tree1a23e881db65a77b80c5eff6236b37f6be1a2fc8 /src/northbridge/intel
parent58c68d56de30c8681facbbecf7a2f08c8ebb3355 (diff)
nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
The code can't handle cyclic zero runs. Make sure it will never wrap around by setting the top-most bit to constant one. Fixes "Mini channel test failed (2)". Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13853 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b81860264d..65282d2848 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -3435,9 +3435,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
u32 raw_statistics[MAX_TIMC + 1];
int statistics[MAX_TIMC + 1];
+ /* Make sure rn.start < rn.end */
+ statistics[MAX_TIMC] = 1;
+
fill_pattern5(ctrl, channel, pat);
write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
- for (timC = 0; timC < MAX_TIMC + 1; timC++) {
+ for (timC = 0; timC < MAX_TIMC; timC++) {
FOR_ALL_LANES
ctrl->timings[channel][slotrank].lanes[lane].timC = timC;
program_timings(ctrl, channel);
@@ -3449,10 +3452,11 @@ static void discover_timC_write(ramctr_timing * ctrl)
}
FOR_ALL_LANES {
struct run rn;
- for (timC = 0; timC <= MAX_TIMC; timC++)
+ for (timC = 0; timC < MAX_TIMC; timC++)
statistics[timC] =
!!(raw_statistics[timC] &
(1 << lane));
+
rn = get_longest_zero_run(statistics,
MAX_TIMC + 1);
if (rn.all)