diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-21 21:03:46 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 16:30:42 +0000 |
| commit | 6642b44b292c9cbbf83905ed89aa00b19c79ddca (patch) | |
| tree | c57446c4a59c9729332792eb4a2657c2a06510c3 /src/northbridge/intel | |
| parent | 9d7431c848d9f8ec35d9407521164b2b5bb83bf0 (diff) | |
nb/intel/ironlake: Add more host bridge PCI IDs
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
The current coreboot code seems to be able to change the device ID
of the host bridge, but it seems to be missing a warm reset so that
the device ID changes. Account for the 'mysterious' device IDs in
the northbridge driver, so that booting an OS has a chance to work.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Although only Arrandale is known to work, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/ironlake/northbridge.c | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 0047c2f849..68dcf7d13f 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -202,10 +202,34 @@ static struct device_operations mc_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const struct pci_driver mc_driver_ard __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Arrandale DRAM controller */ +/* + * The host bridge PCI device ID can be changed by the firmware. There + * is no documentation about it, though. There's 'official' IDs, which + * appear in spec updates and Windows drivers, and 'mysterious' IDs, + * which Intel doesn't want OSes to know about and thus are not listed. + * + * The current coreboot code seems to be able to change the device ID + * of the host bridge, but it seems to be missing a warm reset so that + * the device ID changes. Account for the 'mysterious' device IDs in + * the northbridge driver, so that booting an OS has a chance to work. + */ +static const unsigned short pci_device_ids[] = { + /* 'Official' DIDs */ + 0x0040, /* Clarkdale */ + 0x0044, /* Arrandale */ + 0x0048, /* Unknown, but it appears in OS drivers and raminit */ + + /* Mysterious DIDs, taken from Linux' intel-agp driver */ + 0x0062, /* Arrandale A-? */ + 0x0069, /* Clarkdale K-0 */ + 0x006a, /* Arrandale K-0 */ + 0 +}; + +static const struct pci_driver mc_driver_ilk __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; static struct device_operations cpu_bus_ops = { |