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authorStefan Reinauer <stepan@coresystems.de>2010-04-14 11:40:34 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-14 11:40:34 +0000
commit5d3dee8334c2303434d7b00bec3aad4911120ac1 (patch)
tree38fd30e2473dc76d9cd64092133127934f184e9e /src/northbridge/intel
parent4154c668f24da79672099dfac06f5263c415fee0 (diff)
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7501/raminit.c9
-rw-r--r--src/northbridge/intel/i3100/raminit.c9
2 files changed, 4 insertions, 14 deletions
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 70a692cd92..371262251a 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -1919,14 +1919,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
RAM_DEBUG_MESSAGE("Reading SPD data...\n");
- //activate_spd_rom(ctrl); Not necessary for this chipset
-
- dimm_mask = spd_get_supported_dimms(ctrl);
+ dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
print_debug("No usable memory for this controller\n");
- } else {
-
+ } else {
enable_e7501_clocks(dimm_mask);
RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
@@ -1967,7 +1964,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
DUMPNORTH();
ram_set_rcomp_regs();
- ram_set_d0f0_regs();
+ ram_set_d0f0_regs();
}
/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index fa44d599f1..242dcf9105 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -88,7 +88,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
{
/* Calculate the log base 2 size of a DIMM in bits */
struct dimm_size sz;
- int value, low, ddr2;
+ int value, low;
sz.side1 = 0;
sz.side2 = 0;
@@ -594,8 +594,6 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
- val_err:
- die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -715,7 +713,6 @@ static void set_receive_enable(const struct mem_controller *ctrl)
u32 dimm;
u32 edge;
int32_t data32;
- u32 data32_dram;
u32 dcal_data32_0;
u32 dcal_data32_1;
u32 dcal_data32_2;
@@ -948,10 +945,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
u32 data32;
u32 mode_reg;
u32 *iptr;
- volatile u32 *iptrv;
- msr_t msr;
- u32 scratch;
- u8 byte;
u16 data16;
static const struct {
u32 clkgr[4];