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authorAngel Pons <th3fanbus@gmail.com>2020-09-14 19:06:53 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-21 08:04:57 +0000
commit55f11e29e4a04fbd66da310a32733c3b60e7df42 (patch)
treed8173ad5abc49f9051f49c6aa9bb8bed30b6310d /src/northbridge/intel
parent36592bfe40170e56428e20a58226adf16783a26c (diff)
nb/intel/ironlake: Clean up `send_heci_uma_message` signature
The only raminfo field it needs is `memory_reserved_for_heci_mb`. So, pass in that value directly. As it's read-only, make it const as well. Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45365 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/ironlake/raminit.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index a3885a3ebf..38a879c52a 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1763,7 +1763,7 @@ recv_heci_message(u32 *message, u32 *message_size)
return -1;
}
-static void send_heci_uma_message(struct raminfo *info, const u64 heci_uma_addr)
+static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size)
{
volatile struct uma_reply {
u8 group_id;
@@ -1789,7 +1789,7 @@ static void send_heci_uma_message(struct raminfo *info, const u64 heci_uma_addr)
} __packed msg = {
0, MKHI_SET_UMA, 0, 0,
0x82,
- heci_uma_addr, info->memory_reserved_for_heci_mb, 0};
+ heci_uma_addr, heci_uma_size, 0};
u32 reply_size;
send_heci_message((u8 *) & msg, sizeof(msg), 0, 7);
@@ -1840,7 +1840,7 @@ static void setup_heci_uma(struct raminfo *info)
MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb;
- send_heci_uma_message(info, heci_uma_addr);
+ send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb);
pci_write_config32(HECIDEV, 0x10, 0x0);
pci_write_config8(HECIDEV, 0x4, 0x0);