diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-11 13:42:20 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-12 19:48:26 +0000 |
| commit | 33b59c9170a66a7f6d9c26ccf664714ea81d218d (patch) | |
| tree | f5b71768d08472e1f2f5bea638099601b8e24a37 /src/northbridge/intel | |
| parent | 3b0a4899d8ded1ee9bec1d431d91f431291e3eb0 (diff) | |
haswell: Drop `mainboard_fill_pei_data`
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.h | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 4 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index adf53ea4b4..ee0af776a9 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -6,15 +6,16 @@ #include <stdint.h> #include "pei_data.h" +/* Mainboard-specific USB configuration */ +extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS]; +extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS]; + /* Optional function to copy SPD data for on-board memory */ void copy_spd(struct pei_data *peid); /* Mainboard callback to fill in the SPD addresses in MRC format */ void mb_get_spd_map(uint8_t spd_map[4]); -/* Necessary function to initialize pei_data with mainboard-specific settings */ -void mainboard_fill_pei_data(struct pei_data *pei_data); - void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index cbb9834763..b77e559801 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -18,6 +18,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> +#include <string.h> /* Copy SPD data for on-board memory */ void __weak copy_spd(struct pei_data *peid) @@ -70,7 +71,8 @@ void mainboard_romstage_entry(void) .usb_xhci_on_resume = cfg->usb_xhci_on_resume, }; - mainboard_fill_pei_data(&pei_data); + memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); + memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); enable_lapic(); |