diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 13:06:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:00:31 +0000 |
| commit | 30931f5a4d67571ab8138777647d1d7f29ca3671 (patch) | |
| tree | cdb09228ea8565f738ef525f40dc683b2c1810b6 /src/northbridge/intel | |
| parent | 0b39379c9c85d693b74ae7e954298bc4760285f3 (diff) | |
sb/intel/lynxpoint: Move S3 check out of `early_pch_init`
Done for consistency with other platforms. This also drops redundant S3
resume logging, as `southbridge_detect_s3_resume` already prints it.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 7b4182e65e..48ba4767e4 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -5,6 +5,7 @@ #include <cf9_reset.h> #include <device/device.h> #include <device/mmio.h> +#include <elog.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> @@ -16,6 +17,7 @@ #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> #include <string.h> @@ -47,8 +49,6 @@ void mainboard_romstage_entry(void) const struct northbridge_intel_haswell_config *cfg = config_of_soc(); - int s3resume; - struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, @@ -76,7 +76,11 @@ void mainboard_romstage_entry(void) enable_lapic(); - s3resume = early_pch_init(); + early_pch_init(); + + const int s3resume = southbridge_detect_s3_resume(); + + elog_boot_notify(s3resume); /* Perform some early chipset initialization required * before RAM initialization can work @@ -84,15 +88,6 @@ void mainboard_romstage_entry(void) haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - if (s3resume) { -#if CONFIG(HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - s3resume = 0; -#endif - } - /* Prepare USB controller early in S3 resume */ if (s3resume) enable_usb_bar(); |