diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-11 10:47:39 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-13 09:58:18 +0000 |
| commit | 2cce24dd4b9aa106d3ac2e5519fc84a435813c09 (patch) | |
| tree | d3e552f846bab0fc47c0c14ad614fe22da881786 /src/northbridge/intel | |
| parent | 216db613a7dfbad3bfb150e3ae9927f5e970cd4c (diff) | |
intel/nehalem: Refactor ACPI S3 detection
Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/nehalem/early_init.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index a5cac7b19a..1f413e3ad1 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -73,22 +73,7 @@ static void nehalem_setup_bars(void) pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif } static void early_cpu_init (void) @@ -134,6 +119,7 @@ void nehalem_early_initialization(int chipset_type) { u32 capid0_a; u8 reg8; + int s3_resume; /* Device ID Override Enable should be done very early */ capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); @@ -150,6 +136,12 @@ void nehalem_early_initialization(int chipset_type) /* Setup all BARs required for early PCIe and raminit */ nehalem_setup_bars(); + s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); + + if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) + boot_count_increment(); + /* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); @@ -161,7 +153,7 @@ void nehalem_early_initialization(int chipset_type) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Magic for S3 resume. Must be done early. */ - if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + if (s3_resume) { MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; } |