Make MRC vs native a config rather than making a separate chipset for it.

Tested by making lenovo x230 configurable despite pretty MRC bugs.

Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 19 insertions, 28 deletions

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 9d4d089dd1..5b7284872a 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -13,12 +13,6 @@
 ## GNU General Public License for more details.
 ##
 
-config NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
-	bool
-	select MMCONF_SUPPORT
-	select MMCONF_SUPPORT_DEFAULT
-	select CPU_INTEL_MODEL_206AX
-	select INTEL_GMA_ACPI
 
 config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	bool
@@ -28,13 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
 
-config NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
-	bool
-	select MMCONF_SUPPORT
-	select MMCONF_SUPPORT_DEFAULT
-	select CPU_INTEL_MODEL_306AX
-	select INTEL_GMA_ACPI
-
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
 	select MMCONF_SUPPORT
@@ -43,7 +30,14 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
 
-if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
+if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config USE_NATIVE_RAMINIT
+	bool "Use native raminit"
+	default y
+	help
+	  Select if you want to use coreboot implementation of raminit rather than
+	  System Agent/MRC.bin. You should answer Y.
 
 config CBFS_SIZE
 	hex
@@ -79,10 +73,8 @@ config MRC_CACHE_SIZE
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
-	default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
-	default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE
-	default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
+	default 0xff7e0000 if !USE_NATIVE_RAMINIT
+	default 0xfefe0000 if USE_NATIVE_RAMINIT
 
 config DCACHE_RAM_SIZE
 	hex
@@ -98,7 +90,7 @@ config DCACHE_RAM_MRC_VAR_SIZE
 
 config HAVE_MRC
 	bool "Add a System Agent binary"
-	depends on !NORTHBRIDGE_INTEL_IVYBRIDGE && !NORTHBRIDGE_INTEL_SANDYBRIDGE
+	depends on !USE_NATIVE_RAMINIT
 	help
 	  Select this option to add a System Agent binary to
 	  the resulting coreboot image.
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 90abe4dab6..7a3c498b2c 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -13,7 +13,7 @@
 # GNU General Public License for more details.
 #
 
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC),y)
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y)
 
 ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
@@ -25,12 +25,12 @@ ramstage-y += acpi.c
 ramstage-y += mrccache.c
 
 romstage-y += ram_calc.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c
+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
+romstage-y += raminit.c
+romstage-y += ../../../device/dram/ddr3.c
+else
+romstage-y += raminit_mrc.c
+endif
 romstage-y += romstage.c
 romstage-y += mrccache.c
 romstage-y += iommu.c
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 04db608f83..7b367c5b69 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -70,8 +70,7 @@ void main(unsigned long bist)
 	mainboard_config_superio();
 
 	/* USB is inited in MRC if MRC is used.  */
-	if (!(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
-	      || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC)) {
+	if (CONFIG_USE_NATIVE_RAMINIT) {
 		early_usb_init(mainboard_usb_ports);
 	}