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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-10 19:12:53 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-16 20:40:41 +0100 |
| commit | 13a845acb3aee15dad1b4d66027731baba659e0e (patch) | |
| tree | 11b3432828f9901c6959ea83065ce7cbda3004e9 /src/northbridge/intel | |
| parent | cb0dd58b37b22f7731cd81da8024934040fafdc0 (diff) | |
Intel FSP: Move to DYNAMIC_CBMEM
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT
is not enough to disable CBMEM console for romstage on these platforms.
To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.
Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25208..a95d7368b5 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -243,9 +243,16 @@ static void pci_domain_set_resources(device_t dev) add_fixed_resources(dev, 6); assign_resources(dev->link_list); +} + +unsigned long get_top_of_ram(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - /* Leave some space for the HOB data above CBMem */ - set_top_of_ram((tomk - 2048) * 1024); + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); + tom -= 0x200000; /* 2MB for FSP HOB */ + return (unsigned long) tom; } /* TODO We could determine how many PCIe busses we need in |