diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-10 19:22:31 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:38:29 +0000 |
| commit | 11c6b8b53182c5c83095136712f3d38eb5c1dd6a (patch) | |
| tree | 71bf26998c487dd0528cd7f720e2b385be93e211 /src/northbridge/intel | |
| parent | b8b41338aae9acfa2a49c64d8e57a95653aef610 (diff) | |
nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 4 |
4 files changed, 6 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e3f9aec266..5b9284220b 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -25,6 +25,9 @@ config HASWELL_VBOOT_IN_BOOTBLOCK binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done. +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c00c801ee1..501caf17f1 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -14,7 +14,6 @@ #include <boot/tables.h> #include <security/intel/txt/txt_register.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" #include "haswell.h" @@ -336,9 +335,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (CONFIG(CHROMEOS_RAMOOPS)) - chromeos_reserve_ram_oops(dev, index++); - *resource_cnt = index; } diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 215560f84b..e06bdac4c1 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -32,6 +32,9 @@ config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done. +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ead3c67c0d..fbed687f60 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -14,7 +14,6 @@ #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm_reloc.h> -#include <vendorcode/google/chromeos/chromeos.h> /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -68,9 +67,6 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); - if (CONFIG(CHROMEOS_RAMOOPS)) - chromeos_reserve_ram_oops(dev, index++); - if (is_sandybridge()) { /* Required for SandyBridge sighting 3715511 */ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |