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authorVincent Palatin <vpalatin@chromium.org>2012-03-28 16:10:29 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-05-01 20:04:24 +0200
commit0ff99b70f5c5b6797507d3f152c5d452e1210110 (patch)
tree32345e23a3e71ce520b5cd6fd8dfa87fcfff0de4 /src/northbridge/intel
parent459b7777fe871c5c9bd6636b1b13efc784129e31 (diff)
Modify DMI init for IvyBridge
The ASPM setting for the Direct Media Interface should no longer be done on Ivybridge/PantherPoint based systems. Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/969 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index e3334c45a6..b1f7c72132 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -347,10 +347,12 @@ static void northbridge_dmi_init(struct device *dev)
DMIBAR32(0x1d0) = 0xffffffff;
/* Steps prior to DMI ASPM */
- reg32 = DMIBAR32(0x250);
- reg32 &= ~((1 << 22)|(1 << 20));
- reg32 |= (1 << 21);
- DMIBAR32(0x250) = reg32;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ reg32 = DMIBAR32(0x250);
+ reg32 &= ~((1 << 22)|(1 << 20));
+ reg32 |= (1 << 21);
+ DMIBAR32(0x250) = reg32;
+ }
reg32 = DMIBAR32(0x238);
reg32 |= (1 << 29);
@@ -372,9 +374,11 @@ static void northbridge_dmi_init(struct device *dev)
}
/* Enable ASPM on SNB link, should happen before PCH link */
- reg32 = DMIBAR32(0xd04);
- reg32 |= (1 << 4);
- DMIBAR32(0xd04) = reg32;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ reg32 = DMIBAR32(0xd04);
+ reg32 |= (1 << 4);
+ DMIBAR32(0xd04) = reg32;
+ }
reg32 = DMIBAR32(0x88);
reg32 |= (1 << 1) | (1 << 0);