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authorStefan Reinauer <stepan@coresystems.de>2010-03-22 11:42:32 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-22 11:42:32 +0000
commitc02b4fc9db3c3c1e263027382697b566127f66bb (patch)
tree11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/northbridge/intel
parent27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff)
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7501/debug.c32
-rw-r--r--src/northbridge/intel/e7520/northbridge.c2
-rw-r--r--src/northbridge/intel/e7520/pciexp_porta.c4
-rw-r--r--src/northbridge/intel/e7525/northbridge.c2
-rw-r--r--src/northbridge/intel/i3100/northbridge.c2
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta.c4
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta_ep80579.c8
-rw-r--r--src/northbridge/intel/i440bx/debug.c12
-rw-r--r--src/northbridge/intel/i440bx/northbridge.c4
-rw-r--r--src/northbridge/intel/i440lx/northbridge.c4
-rw-r--r--src/northbridge/intel/i440lx/raminit.c2
-rw-r--r--src/northbridge/intel/i82810/northbridge.c10
-rw-r--r--src/northbridge/intel/i82830/i82830_smihandler.c106
-rw-r--r--src/northbridge/intel/i82830/northbridge.c10
-rw-r--r--src/northbridge/intel/i82830/vga.c16
-rw-r--r--src/northbridge/intel/i855/northbridge.c12
-rw-r--r--src/northbridge/intel/i945/debug.c26
-rw-r--r--src/northbridge/intel/i945/early_init.c154
-rw-r--r--src/northbridge/intel/i945/northbridge.c30
-rw-r--r--src/northbridge/intel/i945/raminit.c176
-rw-r--r--src/northbridge/intel/i945/rcven.c30
21 files changed, 322 insertions, 324 deletions
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 75ed33ea40..cc82e2f60d 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -40,7 +40,7 @@ static void dump_pci_device(unsigned dev)
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
- printk_debug("\r\n%02x:",i);
+ printk(BIOS_DEBUG, "\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
@@ -49,7 +49,7 @@ static void dump_pci_device(unsigned dev)
}
val = pci_read_config8(dev, i);
#if CONFIG_USE_INIT
- printk_debug(" %02x", val);
+ printk(BIOS_DEBUG, " %02x", val);
#else
print_debug_char(' ');
print_debug_hex8(val);
@@ -102,7 +102,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
if (device) {
int j;
#if CONFIG_USE_INIT
- printk_debug("dimm: %02x.0: %02x", i, device);
+ printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
@@ -114,7 +114,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
- printk_debug("\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
@@ -127,7 +127,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
byte = status & 0xff;
#if CONFIG_USE_INIT
- printk_debug("%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
@@ -139,7 +139,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
if (device) {
int j;
#if CONFIG_USE_INIT
- printk_debug("dimm: %02x.1: %02x", i, device);
+ printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else`
print_debug("dimm: ");
print_debug_hex8(i);
@@ -151,7 +151,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
- printk_debug("\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
@@ -164,7 +164,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
byte = status & 0xff;
#if CONFIG_USE_INIT
- printk_debug("%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
@@ -182,7 +182,7 @@ static void dump_smbus_registers(void)
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_INIT
- printk_debug("smbus: %02x", device);
+ printk(BIOS_DEBUG, "smbus: %02x", device);
#else
print_debug("smbus: ");
print_debug_hex8(device);
@@ -196,7 +196,7 @@ static void dump_smbus_registers(void)
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
- printk_debug("\r\n%02x: ",j);
+ printk(BIOS_DEBUG, "\r\n%02x: ",j);
#else
print_debug("\r\n");
print_debug_hex8(j);
@@ -205,7 +205,7 @@ static void dump_smbus_registers(void)
}
byte = status & 0xff;
#if CONFIG_USE_INIT
- printk_debug("%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
@@ -220,7 +220,7 @@ static void dump_io_resources(unsigned port)
int i;
#if CONFIG_USE_INIT
- printk_debug("%04x:\r\n", port);
+ printk(BIOS_DEBUG, "%04x:\r\n", port);
#else
print_debug_hex16(port);
print_debug(":\r\n");
@@ -229,7 +229,7 @@ static void dump_io_resources(unsigned port)
uint8_t val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
- printk_debug("%02x:", i);
+ printk(BIOS_DEBUG, "%02x:", i);
#else
print_debug_hex8(i);
print_debug_char(':');
@@ -237,7 +237,7 @@ static void dump_io_resources(unsigned port)
}
val = inb(port);
#if CONFIG_USE_INIT
- printk_debug(" %02x",val);
+ printk(BIOS_DEBUG, " %02x",val);
#else
print_debug_char(' ');
print_debug_hex8(val);
@@ -256,7 +256,7 @@ static void dump_mem(unsigned start, unsigned end)
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_INIT
- printk_debug("\r\n%08x:", i);
+ printk(BIOS_DEBUG, "\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug_hex32(i);
@@ -264,7 +264,7 @@ static void dump_mem(unsigned start, unsigned end)
#endif
}
#if CONFIG_USE_INIT
- printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+ printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index fd9b094469..efb7f0263b 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = find_pci_tolm(&dev->link[0]);
#if 1
- printk_debug("PCI mem marker = %x\n", pci_tolm);
+ printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
#endif
/* FIXME Me temporary hack */
if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c
index 70e58076a7..07440e368e 100644
--- a/src/northbridge/intel/e7520/pciexp_porta.c
+++ b/src/northbridge/intel/e7520/pciexp_porta.c
@@ -30,12 +30,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
int flag = 0;
do {
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
if((val & (1<<10) )&&(!flag)) { /* training error */
ctl = pci_read_config16(dev, 0x74);
pci_write_config16(dev, 0x74, (ctl | (1<<5)));
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta reset 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
flag=1;
hard_reset();
}
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 3c483a143b..02bf119b96 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = find_pci_tolm(&dev->link[0]);
#if 1
- printk_debug("PCI mem marker = %x\n", pci_tolm);
+ printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
#endif
/* FIXME Me temporary hack */
if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 0a04faf61a..195790f8cd 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -86,7 +86,7 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = find_pci_tolm(&dev->link[0]);
#if 1
- printk_debug("PCI mem marker = %x\n", pci_tolm);
+ printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
#endif
/* FIXME Me temporary hack */
if(pci_tolm > 0xe0000000)
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c
index b94094ed17..df375ee5f7 100644
--- a/src/northbridge/intel/i3100/pciexp_porta.c
+++ b/src/northbridge/intel/i3100/pciexp_porta.c
@@ -52,12 +52,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
int flag = 0;
do {
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
if ((val & (1<<10)) && (!flag)) { /* training error */
ctl = pci_read_config16(dev, 0x74);
pci_write_config16(dev, 0x74, (ctl | (1<<5)));
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta reset 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
flag=1;
hard_reset();
}
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index d51227c0aa..aff287cb56 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -44,7 +44,7 @@ static void pcie_init(struct device *dev)
pci_write_config32(dev, 0x3c, config->intrline);
}
- printk_spew("configure PCIe port as \"Slot Implemented\"\n");
+ printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");
val = pci_read_config16(dev, 0x66);
val &= ~(1<<8);
val |= 1<<8;
@@ -58,7 +58,7 @@ static void pcie_bus_enable_resources(struct device *dev)
{
u8 val8;
if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
- printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n");
+ printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");
pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);
dev->command |= PCI_COMMAND_IO;
@@ -76,12 +76,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
int flag = 0;
do {
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);
if ((val & (1<<11)) && (!flag)) { /* training error */
ctl = pci_read_config16(dev, 0x74);
pci_write_config16(dev, 0x74, (ctl | (1<<5)));
val = pci_read_config16(dev, 0x76);
- printk_debug("pcie porta reset 0x76: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);
flag=1;
hard_reset();
}
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index 35ab611583..fab224dc85 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -39,25 +39,25 @@ void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- printk_debug("dimm %02x", device);
+ printk(BIOS_DEBUG, "dimm %02x", device);
for(i = 0; (i < 256) && (status == 0); i++) {
unsigned char byte;
if ((i % 20) == 0) {
- printk_debug("\n%3d: ", i);
+ printk(BIOS_DEBUG, "\n%3d: ", i);
}
status = smbus_read_byte(device, i, &byte);
if (status != 0) {
- printk_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
continue;
}
- printk_debug("%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
}
device += SMBUS_MEM_DEVICE_INC;
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 4431aafaf8..772ab1c8f3 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -15,7 +15,7 @@
static void northbridge_init(device_t dev)
{
- printk_spew("Northbridge Init\n");
+ printk(BIOS_SPEW, "Northbridge Init\n");
}
static struct device_operations northbridge_operations = {
@@ -97,7 +97,7 @@ static void i440bx_domain_set_resources(device_t dev)
/* Convert to KB. */
tomk *= (8 * 1024);
- printk_debug("Setting RAM size to %ld MB\n", tomk / 1024);
+ printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
/* Compute the top of low memory. */
tolmk = pci_tolm / 1024;
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c
index 41cc43bbc4..ebe38afd51 100644
--- a/src/northbridge/intel/i440lx/northbridge.c
+++ b/src/northbridge/intel/i440lx/northbridge.c
@@ -43,7 +43,7 @@
*/
static void northbridge_init(device_t dev)
{
- printk_spew("Northbridge Init\n");
+ printk(BIOS_SPEW, "Northbridge Init\n");
}
static struct device_operations northbridge_operations = {
@@ -125,7 +125,7 @@ static void i440lx_domain_set_resources(device_t dev)
/* Convert to KB. */
tomk *= (8 * 1024);
- printk_debug("Setting RAM size to %lu MB\n", tomk / 1024);
+ printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
/* Compute the top of low memory. */
tolmk = pci_tolm / 1024;
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 4c171ef92d..5d07441dde 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -244,7 +244,7 @@ static void sdram_set_registers(void)
#if 0
uint16_t reg16;
reg16 = pci_read_config16(NB, PACCFG);
- printk_debug("i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+ printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
#endif
PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 2129c1b6af..23e7acffbd 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -34,7 +34,7 @@
static void northbridge_init(device_t dev)
{
- printk_spew("Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
@@ -142,7 +142,7 @@ static void pci_domain_set_resources(device_t dev)
drp_value = drp_value >> 4; // >>= 4; //? mess with later
tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
- printk_debug("Setting RAM size to %d MB\n", tomk);
+ printk(BIOS_DEBUG, "Setting RAM size to %d MB\n", tomk);
/* Convert tomk from MB to KB. */
tomk = tomk << 10;
@@ -151,12 +151,12 @@ static void pci_domain_set_resources(device_t dev)
/* Check for VGA reserved memory. */
if (CONFIG_VIDEO_MB == 512) {
tomk -= 512;
- printk_debug("Allocating %s RAM for VGA\n", "512KB");
+ printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "512KB");
} else if (CONFIG_VIDEO_MB == 1) {
tomk -= 1024 ;
- printk_debug("Allocating %s RAM for VGA\n", "1MB");
+ printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "1MB");
} else {
- printk_debug("Allocating %s RAM for VGA\n", "0MB");
+ printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "0MB");
}
#endif
diff --git a/src/northbridge/intel/i82830/i82830_smihandler.c b/src/northbridge/intel/i82830/i82830_smihandler.c
index 1c45927a86..e53d283b4b 100644
--- a/src/northbridge/intel/i82830/i82830_smihandler.c
+++ b/src/northbridge/intel/i82830/i82830_smihandler.c
@@ -80,17 +80,17 @@ typedef struct {
static void
dump(u8 * addr, u32 len)
{
- printk_debug("\n%s(%p, %x):\n", __func__, addr, len);
+ printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
while (len) {
unsigned int tmpCnt = len;
unsigned char x;
if (tmpCnt > 8)
tmpCnt = 8;
- printk_debug("\n%p: ", addr);
+ printk(BIOS_DEBUG, "\n%p: ", addr);
// print hex
while (tmpCnt--) {
x = *addr++;
- printk_debug("%02x ", x);
+ printk(BIOS_DEBUG, "%02x ", x);
}
tmpCnt = len;
if (tmpCnt > 8)
@@ -105,10 +105,10 @@ dump(u8 * addr, u32 len)
//non-printable char
x = '.';
}
- printk_debug("%c", x);
+ printk(BIOS_DEBUG, "%c", x);
}
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
@@ -150,19 +150,19 @@ typedef struct {
static void mbi_call(u8 subf, banner_id_t *banner_id)
{
#ifdef DEBUG_SMI_I82830
- printk_debug("MBI\n");
- printk_debug("|- sub function %x\n", subf);
- printk_debug("|- banner id @ %x\n", (u32)banner_id);
- printk_debug("| |- mhid %x\n", banner_id->mhid);
- printk_debug("| |- function %x\n", banner_id->function);
- printk_debug("| |- return status %x\n", banner_id->retsts);
- printk_debug("| |- rfu %x\n", banner_id->rfu);
+ printk(BIOS_DEBUG, "MBI\n");
+ printk(BIOS_DEBUG, "|- sub function %x\n", subf);
+ printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
+ printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);
+ printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);
+ printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);
+ printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);
#endif
switch(banner_id->function) {
case 0x0001: {
version_t *version;
- printk_debug("|- MBI_QueryInterface\n");
+ printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
version = (version_t *)banner_id;
version->banner.retsts = MSH_OK;
version->versionmajor=1;
@@ -171,18 +171,18 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
break;
}
case 0x0002:
- printk_debug("|- MBI_Attach\n");
- printk_debug("|  |- Not Implemented!\n");
+ printk(BIOS_DEBUG, "|- MBI_Attach\n");
+ printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
break;
case 0x0003:
- printk_debug("|- MBI_Detach\n");
- printk_debug("|  |- Not Implemented!\n");
+ printk(BIOS_DEBUG, "|- MBI_Detach\n");
+ printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
break;
case 0x0201: {
obj_header_t *obj_header = (obj_header_t *)banner_id;
mbi_header_t *mbi_header = NULL;
- printk_debug("|- MBI_GetObjectHeader\n");
- printk_debug("| |- objnum = %d\n", obj_header->objnum);
+ printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
+ printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
int i, count=0;
obj_header->banner.retsts = MSH_IF_NOT_FOUND;
@@ -201,15 +201,15 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
if (obj_header->objnum == count) {
int headerlen = ALIGN(sizeof(mbi_header) + mbi_header->name_len + 15, 16);
#ifdef DEBUG_SMI_I82830
- printk_debug("| |- headerlen = %d\n", headerlen);
+ printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);
#endif
memcpy(&obj_header->header, mbi_header, headerlen);
obj_header->banner.retsts = MSH_OK;
- printk_debug("| |- MBI module '");
+ printk(BIOS_DEBUG, "| |- MBI module '");
int j;
for (j=0; j < mbi_header->name_len && mbi_header->name[j]; j++)
- printk_debug("%c", mbi_header->name[j]);
- printk_debug("' found.\n");
+ printk(BIOS_DEBUG, "%c", mbi_header->name[j]);
+ printk(BIOS_DEBUG, "' found.\n");
#ifdef DEBUG_SMI_I82830
dump(banner_id, sizeof(obj_header_t) + 16);
#endif
@@ -219,21 +219,21 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
count++;
}
if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
- printk_debug("| |- MBI object #%d not found.\n", obj_header->objnum);
+ printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);
break;
}
case 0x0203: {
get_object_t *getobj = (get_object_t *)banner_id;
mbi_header_t *mbi_header = NULL;
- printk_debug("|- MBI_GetObject\n");
+ printk(BIOS_DEBUG, "|- MBI_GetObject\n");
#ifdef DEBUG_SMI_I82830
- printk_debug("| |- handle = %016lx\n", getobj->handle);
+ printk(BIOS_DEBUG, "| |- handle = %016lx\n", getobj->handle);
#endif
- printk_debug("| |- objnum = %d\n", getobj->objnum);
- printk_debug("| |- start = %x\n", getobj->start);
- printk_debug("| |- numbytes = %x\n", getobj->numbytes);
- printk_debug("| |- buflen = %x\n", getobj->buflen);
- printk_debug("| |- buffer = %x\n", getobj->buffer);
+ printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);
+ printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);
+ printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);
+ printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);
+ printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
int i, count=0;
getobj->banner.retsts = MSH_IF_NOT_FOUND;
@@ -250,7 +250,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16);
if (getobj->objnum == count) {
- printk_debug("| |- len = %x\n", len);
+ printk(BIOS_DEBUG, "| |- len = %x\n", len);
memcpy((void *)(getobj->buffer + OBJ_OFFSET),
((char *)mbi_header) + 0x20 , (len > getobj->buflen ? getobj->buflen : len));
@@ -264,15 +264,15 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
count++;
}
if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
- printk_debug("MBI module %d not found.\n", getobj->objnum);
+ printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
break;
}
default:
- printk_debug("|- function %x\n", banner_id->function);
- printk_debug("| |- Unknown Function!\n");
+ printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
+ printk(BIOS_DEBUG, "| |- Unknown Function!\n");
break;
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
//dump(banner_id, 0x20);
}
@@ -291,7 +291,7 @@ static void smi_interface_call(void)
{
u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
// mmio &= 0xfff80000;
- // printk_debug("mmio=%x\n", mmio);
+ // printk(BIOS_DEBUG, "mmio=%x\n", mmio);
u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
if (!(swsmi & 1))
@@ -301,7 +301,7 @@ static void smi_interface_call(void)
switch ((swsmi>>1) & 0xf) {
case 0:
- printk_debug("Interface Function Presence Test.\n");
+ printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
swsmi = 0;
swsmi &= ~(7 << 5); // Exit: Result
swsmi |= (SMI_IFC_SUCCESS << 5);
@@ -312,11 +312,11 @@ static void smi_interface_call(void)
write32(mmio + 0x71428, 0x494e5443);
return;
case 4:
- printk_debug("Get BIOS Data.\n");
- printk_debug("swsmi=%04x\n", swsmi);
+ printk(BIOS_DEBUG, "Get BIOS Data.\n");
+ printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
break;
case 5:
- printk_debug("Call MBI Functions.\n");
+ printk(BIOS_DEBUG, "Call MBI Functions.\n");
mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
// swsmi = 0x0000;
swsmi &= ~(7 << 5); // Exit: Result
@@ -324,11 +324,11 @@ static void smi_interface_call(void)
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
return;
case 6:
- printk_debug("System BIOS Callbacks.\n");
- printk_debug("swsmi=%04x\n", swsmi);
+ printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
+ printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
break;
default:
- printk_debug("Unknown SMI interface call %04x\n", swsmi);
+ printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
break;
}
@@ -354,15 +354,15 @@ static u16 reset_err_status(void)
static void dump_err_status(u32 errsts)
{
- printk_debug("ERRSTS: ");
- if (errsts & (1 << 12)) printk_debug("MBI ");
- if (errsts & (1 << 9)) printk_debug("LCKF ");
- if (errsts & (1 << 8)) printk_debug("DTF ");
- if (errsts & (1 << 5)) printk_debug("UNSC ");
- if (errsts & (1 << 4)) printk_debug("OOGF ");
- if (errsts & (1 << 3)) printk_debug("IAAF ");
- if (errsts & (1 << 2)) printk_debug("ITTEF ");
- printk_debug("\n");
+ printk(BIOS_DEBUG, "ERRSTS: ");
+ if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
+ if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");
+ if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");
+ if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");
+ if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");
+ if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");
+ if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");
+ printk(BIOS_DEBUG, "\n");
}
void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index da76a5d89b..5cd13b7033 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -35,7 +35,7 @@
static void northbridge_init(device_t dev)
{
- printk_spew("Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
@@ -95,7 +95,7 @@ uint64_t uma_memory_base=0, uma_memory_size=0;
int add_northbridge_resources(struct lb_memory *mem)
{
- printk_debug("Adding IGD UMA memory area\n");
+ printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
@@ -120,10 +120,10 @@ static void pci_domain_set_resources(device_t dev)
if (CONFIG_VIDEO_MB == 512) {
igd_memory = (CONFIG_VIDEO_MB);
- printk_debug("%dKB IGD UMA\n", igd_memory >> 10);
+ printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
} else {
igd_memory = (CONFIG_VIDEO_MB * 1024);
- printk_debug("%dMB IGD UMA\n", igd_memory >> 10);
+ printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
}
/* Get the value of the highest DRB. This tells the end of
@@ -136,7 +136,7 @@ static void pci_domain_set_resources(device_t dev)
/* For reserving UMA memory in the memory map */
uma_memory_base = tomk * 1024ULL;
uma_memory_size = igd_memory * 1024ULL;
- printk_debug("Available memory: %ldKB\n", tomk);
+ printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
/* Compute the top of low memory. */
tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
index ccab697a89..37c967414b 100644
--- a/src/northbridge/intel/i82830/vga.c
+++ b/src/northbridge/intel/i82830/vga.c
@@ -31,21 +31,21 @@
static void vga_init(device_t dev)
{
- printk_info("Starting Graphics Initialization\n");
+ printk(BIOS_INFO, "Starting Graphics Initialization\n");
struct cbfs_file *file = cbfs_find("mbi.bin");
void *mbi = NULL;
unsigned int mbi_len = 0;
if (file) {
if (ntohl(file->type) != CBFS_TYPE_MBI) {
- printk_info( "CBFS: MBI binary is of type %x instead of"
+ printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of"
"type %x\n", file->type, CBFS_TYPE_MBI);
} else {
mbi = (void *) CBFS_SUBHEADER(file);
mbi_len = file->len;
}
} else {
- printk_info( "Could not find MBI.\n");
+ printk(BIOS_INFO, "Could not find MBI.\n");
}
if (mbi && mbi_len) {
@@ -59,7 +59,7 @@ static void vga_init(device_t dev)
}
pci_dev_init(dev);
- printk_info("Graphics Initialization Complete\n");
+ printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -68,7 +68,7 @@ static void vga_init(device_t dev)
#define PIPE_A_TV (1 << 3)
#define PIPE_B_CRT (1 << 8)
#define PIPE_B_TV (1 << 10)
- printk_debug("Enabling TV-Out\n");
+ printk(BIOS_DEBUG, "Enabling TV-Out\n");
void runInt10(void);
M.x86.R_AX = 0x5f64;
M.x86.R_BX = 0x0001; // Set Display Device, force execution
@@ -77,13 +77,13 @@ static void vga_init(device_t dev)
runInt10();
switch (M.x86.R_AX) {
case 0x005f:
- printk_debug("... failed.\n");
+ printk(BIOS_DEBUG, "... failed.\n");
break;
case 0x015f:
- printk_debug("... ok.\n");
+ printk(BIOS_DEBUG, "... ok.\n");
break;
default:
- printk_debug("... not supported.\n");
+ printk(BIOS_DEBUG, "... not supported.\n");
break;
}
#endif
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index e33338ec66..8587754fc1 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -79,13 +79,13 @@ static void pci_domain_set_resources(device_t dev)
device_t mc_dev;
uint32_t pci_tolm;
- printk_debug("Entered with dev vid = %x\n", dev->vendor);
- printk_debug("Entered with dev did = %x\n", dev->device);
+ printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+ printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children->sibling;
- printk_debug("MC dev vendor = %x\n", mc_dev->vendor);
- printk_debug("MC dev device = %x\n", mc_dev->device);
+ printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
+ printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@@ -120,8 +120,8 @@ static void pci_domain_set_resources(device_t dev)
*/
/* Report the memory regions */
- printk_debug("tomk = %d\n", tomk);
- printk_debug("tolmk = %d\n", tolmk);
+ printk(BIOS_DEBUG, "tomk = %d\n", tomk);
+ printk(BIOS_DEBUG, "tolmk = %d\n", tolmk);
idx = 10;
/* avoid pam region */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 4a59fee372..a14d0cec63 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -36,9 +36,9 @@ static void print_pci_devices(void)
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
- printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
(dev >> 15) & 0x1f, (dev >> 12) & 7);
- printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
+ printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
}
}
@@ -46,17 +46,17 @@ static void dump_pci_device(unsigned dev)
{
int i;
- printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for(i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
- printk_debug("%02x:", i);
+ printk(BIOS_DEBUG, "%02x:", i);
}
val = pci_read_config8(dev, i);
- printk_debug(" %02x", val);
+ printk(BIOS_DEBUG, " %02x", val);
if ((i & 0x0f) == 0x0f) {
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
@@ -85,21 +85,21 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- printk_debug("\ndimm %02x", device);
+ printk(BIOS_DEBUG, "\ndimm %02x", device);
for(i = 0; (i < 256) ; i++) {
if ((i % 16) == 0) {
- printk_debug("\n%02x: ", i);
+ printk(BIOS_DEBUG, "\n%02x: ", i);
}
status = smbus_read_byte(device, i);
if (status < 0) {
- printk_debug("bad device: %02x\n", -status);
+ printk(BIOS_DEBUG, "bad device: %02x\n", -status);
break;
}
- printk_debug("%02x ", status);
+ printk(BIOS_DEBUG, "%02x ", status);
}
device += SMBUS_MEM_DEVICE_INC;
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -109,9 +109,9 @@ static void dump_mem(unsigned start, unsigned end)
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
- printk_debug("\n%08x:", i);
+ printk(BIOS_DEBUG, "\n%08x:", i);
}
- printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+ printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
print_debug("\n");
}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d16f77a349..f6cdcca961 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -29,108 +29,108 @@ static void i945m_detect_chipset(void)
{
u8 reg8;
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
switch (reg8) {
case 1:
- printk_info("Mobile Intel(R) 82945GM/GME Express");
+ printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
break;
case 2:
- printk_info("Mobile Intel(R) 82945GMS/GU Express");
+ printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
break;
case 3:
- printk_info("Mobile Intel(R) 82945PM Express");
+ printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
break;
case 5:
- printk_info("Intel(R) 82945GT Express");
+ printk(BIOS_INFO, "Intel(R) 82945GT Express");
break;
case 6:
- printk_info("Mobile Intel(R) 82943/82940GML Express");
+ printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
break;
default:
- printk_info("Unknown (%02x)", reg8); /* Others reserved. */
+ printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */
}
- printk_info(" Chipset\n");
+ printk(BIOS_INFO, " Chipset\n");
- printk_debug("(G)MCH capable of up to FSB ");
+ printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
switch (reg8) {
case 2:
- printk_debug("800 MHz"); /* According to 965 spec */
+ printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
break;
case 3:
- printk_debug("667 MHz");
+ printk(BIOS_DEBUG, "667 MHz");
break;
case 4:
- printk_debug("533 MHz");
+ printk(BIOS_DEBUG, "533 MHz");
break;
default:
- printk_debug("N/A MHz (%02x)", reg8);
+ printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
- printk_debug("(G)MCH capable of ");
+ printk(BIOS_DEBUG, "(G)MCH capable of ");
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
switch (reg8) {
case 2:
- printk_debug("up to DDR2-667");
+ printk(BIOS_DEBUG, "up to DDR2-667");
break;
case 3:
- printk_debug("up to DDR2-533");
+ printk(BIOS_DEBUG, "up to DDR2-533");
break;
case 4:
- printk_debug("DDR2-400");
+ printk(BIOS_DEBUG, "DDR2-400");
break;
default:
- printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
+ printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static void i945_detect_chipset(void)
{
u8 reg8;
- printk_info("\nIntel(R) ");
+ printk(BIOS_INFO, "\nIntel(R) ");
reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
switch (reg8) {
case 0:
case 1:
- printk_info("82945G");
+ printk(BIOS_INFO, "82945G");
break;
case 2:
case 3:
- printk_info("82945P");
+ printk(BIOS_INFO, "82945P");
break;
case 4:
- printk_info("82945GC");
+ printk(BIOS_INFO, "82945GC");
break;
case 5:
- printk_info("82945GZ");
+ printk(BIOS_INFO, "82945GZ");
break;
case 6:
case 7:
- printk_info("82945PL");
+ printk(BIOS_INFO, "82945PL");
break;
default:
break;
}
- printk_info(" Chipset\n");
+ printk(BIOS_INFO, " Chipset\n");
- printk_debug("(G)MCH capable of ");
+ printk(BIOS_DEBUG, "(G)MCH capable of ");
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
switch (reg8) {
case 0:
- printk_debug("up to DDR2-667");
+ printk(BIOS_DEBUG, "up to DDR2-667");
break;
case 3:
- printk_debug("up to DDR2-533");
+ printk(BIOS_DEBUG, "up to DDR2-533");
break;
default:
- printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
+ printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static void i945_setup_bars(void)
@@ -139,11 +139,10 @@ static void i945_setup_bars(void)
/* As of now, we don't have all the A0 workarounds implemented */
if (i945_silicon_revision() == 0)
- printk_info
- ("Warning: i945 silicon revision A0 might not work correctly.\n");
+ printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
/* Setting up Southbridge. In the northbridge code. */
- printk_debug("Setting up static southbridge registers...");
+ printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -152,14 +151,14 @@ static void i945_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
setup_ich7_gpios();
- printk_debug(" done.\n");
+ printk(BIOS_DEBUG, " done.\n");
- printk_debug("Disabling Watchdog reboot...");
+ printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
- printk_debug(" done.\n");
+ printk(BIOS_DEBUG, " done.\n");
- printk_debug("Setting up static northbridge registers...");
+ printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
@@ -182,16 +181,16 @@ static void i945_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- printk_debug(" done.\n");
+ printk(BIOS_DEBUG, " done.\n");
/* Wait for MCH BAR to come up */
- printk_debug("Waiting for MCHBAR to come up...");
+ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */
do {
reg8 = *(volatile u8 *)0xfed40000;
} while (!(reg8 & 0x80));
}
- printk_debug("ok\n");
+ printk(BIOS_DEBUG, "ok\n");
}
static void i945_setup_egress_port(void)
@@ -199,7 +198,7 @@ static void i945_setup_egress_port(void)
u32 reg32;
u32 timeout;
- printk_debug("Setting up Egress Port RCRB\n");
+ printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
/* Egress Port Virtual Channel 0 Configuration */
@@ -267,26 +266,26 @@ static void i945_setup_egress_port(void)
EPBAR32(EPVC1RCTL) |= (1 << 16);
EPBAR32(EPVC1RCTL) |= (1 << 16);
- printk_debug("Loading port arbitration table ...");
+ printk(BIOS_DEBUG, "Loading port arbitration table ...");
/* Loop until bit 0 becomes 0 */
timeout = 0x7fffff;
while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
if (!timeout)
- printk_debug("timeout!\n");
+ printk(BIOS_DEBUG, "timeout!\n");
else
- printk_debug("ok\n");
+ printk(BIOS_DEBUG, "ok\n");
/* Now enable VC1 */
EPBAR32(EPVC1RCTL) |= (1 << 31);
- printk_debug("Wait for VC1 negotiation ...");
+ printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7fff;
while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
if (!timeout)
- printk_debug("timeout!\n");
+ printk(BIOS_DEBUG, "timeout!\n");
else
- printk_debug("ok\n");
+ printk(BIOS_DEBUG, "ok\n");
}
@@ -348,7 +347,7 @@ static void i945_setup_dmi_rcrb(void)
int activate_aspm = 1;
- printk_debug("Setting up DMI RCRB\n");
+ printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
/* Virtual Channel 0 Configuration */
reg32 = DMIBAR32(DMIVC0RCTL0);
@@ -373,14 +372,14 @@ static void i945_setup_dmi_rcrb(void)
/* Now enable VC1 */
DMIBAR32(DMIVC1RCTL) |= (1 << 31);
- printk_debug("Wait for VC1 negotiation ...");
+ printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7ffff;
while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
if (!timeout)
- printk_debug("timeout!\n");
+ printk(BIOS_DEBUG, "timeout!\n");
else
- printk_debug("done..\n");
+ printk(BIOS_DEBUG, "done..\n");
#if 1
/* Enable Active State Power Management (ASPM) L0 state */
@@ -425,10 +424,10 @@ static void i945_setup_dmi_rcrb(void)
DMIBAR32(0x204) = reg32;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */
- printk_debug("Internal graphics: enabled\n");
+ printk(BIOS_DEBUG, "Internal graphics: enabled\n");
DMIBAR32(0x200) |= (1 << 21);
} else {
- printk_debug("Internal graphics: disabled\n");
+ printk(BIOS_DEBUG, "Internal graphics: disabled\n");
DMIBAR32(0x200) &= ~(1 << 21);
}
@@ -474,13 +473,13 @@ static void i945_setup_dmi_rcrb(void)
}
/* wait for bit toggle to 0 */
- printk_debug("Waiting for DMI hardware...");
+ printk(BIOS_DEBUG, "Waiting for DMI hardware...");
timeout = 0x7fffff;
while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
if (!timeout)
- printk_debug("timeout!\n");
+ printk(BIOS_DEBUG, "timeout!\n");
else
- printk_debug("ok\n");
+ printk(BIOS_DEBUG, "ok\n");
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
@@ -495,8 +494,7 @@ static void i945_setup_dmi_rcrb(void)
if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) {
if ((MCHBAR32(0x214) & 0xf) != 0x3) {
- printk_info
- ("DMI link requires A1 stepping workaround. Rebooting.\n");
+ printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
reg32 = DMIBAR32(0x224);
reg32 &= ~(7 << 0);
reg32 |= (3 << 0);
@@ -515,7 +513,7 @@ static void i945_setup_pci_express_x16(void)
u8 reg8;
- printk_debug("Enabling PCI Express x16 Link\n");
+ printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
reg16 |= DEVEN_D1F0;
@@ -540,7 +538,7 @@ static void i945_setup_pci_express_x16(void)
pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
- printk_debug("SLOTSTS: %04x\n", reg16);
+ printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
if (!(reg16 & 0x48)) {
goto disable_pciexpress_x16_link;
}
@@ -576,18 +574,18 @@ static void i945_setup_pci_express_x16(void)
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
/* Wait for training to succeed */
- printk_debug("PCIe link training ...");
+ printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
- printk_debug(" Detected PCIe device %04x:%04x\n",
+ printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
reg32 & 0xffff, reg32 >> 16);
} else {
- printk_debug(" timeout!\n");
+ printk(BIOS_DEBUG, " timeout!\n");
- printk_debug("Restrain PCIe port to x1\n");
+ printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
reg32 &= ~(0xf << 1);
@@ -601,17 +599,17 @@ static void i945_setup_pci_express_x16(void)
reg16 &= ~(1 << 6);
pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
- printk_debug("PCIe link training ...");
+ printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
- printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+ printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
reg32 & 0xffff, reg32 >> 16);
} else {
- printk_debug(" timeout!\n");
- printk_debug("Disabling PCIe x16 port completely.\n");
+ printk(BIOS_DEBUG, " timeout!\n");
+ printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
goto disable_pciexpress_x16_link;
}
}
@@ -620,7 +618,7 @@ static void i945_setup_pci_express_x16(void)
reg16 >>= 4;
reg16 &= 0x3f;
/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
- printk_debug("PCIe x%d link training succeeded.\n", reg16);
+ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
reg32 &= 0xfffffc00; /* clear [9:0] */
@@ -633,9 +631,9 @@ static void i945_setup_pci_express_x16(void)
}
reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
- printk_debug("PCIe device class: %06x\n", reg32);
+ printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
if (reg32 == 0x030000) {
- printk_debug("PCIe device is VGA. Disabling IGD.\n");
+ printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
reg16 = (1 << 1);
pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
@@ -758,7 +756,7 @@ static void i945_setup_pci_express_x16(void)
disable_pciexpress_x16_link:
/* For now we just disable the x16 link */
- printk_debug("Disabling PCI Express x16 Link\n");
+ printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
@@ -774,14 +772,14 @@ disable_pciexpress_x16_link:
reg16 &= ~(1 << 6);
pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
- printk_debug("Wait for link to enter detect state... ");
+ printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;
for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
(reg32 & 0x000f0000) && --timeout;) ;
if (!timeout)
- printk_debug("timeout!\n");
+ printk(BIOS_DEBUG, "timeout!\n");
else
- printk_debug("ok\n");
+ printk(BIOS_DEBUG, "ok\n");
/* Finally: Disable the PCI config header */
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
@@ -793,7 +791,7 @@ static void i945_setup_root_complex_topology(void)
{
u32 reg32;
- printk_debug("Setting up Root Complex Topology\n");
+ printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
/* Egress Port Root Topology */
reg32 = EPBAR32(EPESD);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 5f71e19a90..1f5a0359c4 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -75,11 +75,11 @@ int add_northbridge_resources(struct lb_memory *mem)
{
u32 pcie_config_base, pcie_config_size;
- printk_debug("Adding UMA memory area\n");
+ printk(BIOS_DEBUG, "Adding UMA memory area\n");
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
- printk_debug("Adding PCIe config bar\n");
+ printk(BIOS_DEBUG, "Adding PCIe config bar\n");
get_pcie_bar(&pcie_config_base, &pcie_config_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
pcie_config_base, pcie_config_size);
@@ -140,13 +140,13 @@ static void pci_domain_set_resources(device_t dev)
* this way?
*/
pci_tolm = find_pci_tolm(&dev->link[0]);
- printk_debug("pci_tolm: 0x%x\n", pci_tolm);
+ printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
- printk_spew("Base of stolen memory: 0x%08x\n",
+ printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
- printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
+ printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
tomk = tolud << 14;
@@ -154,7 +154,7 @@ static void pci_domain_set_resources(device_t dev)
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
if (reg8 & 1) {
int tseg_size = 0;
- printk_debug("TSEG decoded, subtracting ");
+ printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
reg8 >>= 1;
reg8 &= 3;
switch (reg8) {
@@ -169,14 +169,14 @@ static void pci_domain_set_resources(device_t dev)
break; /* TSEG = 8M */
}
- printk_debug("%dM\n", tseg_size >> 10);
+ printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
tomk -= tseg_size;
}
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
if (!(reg16 & 2)) {
int uma_size = 0;
- printk_debug("IGD decoded, subtracting ");
+ printk(BIOS_DEBUG, "IGD decoded, subtracting ");
reg16 >>= 4;
reg16 &= 7;
switch (reg16) {
@@ -188,7 +188,7 @@ static void pci_domain_set_resources(device_t dev)
break;
}
- printk_debug("%dM UMA\n", uma_size >> 10);
+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
tomk -= uma_size;
/* For reserving UMA memory in the memory map */
@@ -199,8 +199,8 @@ static void pci_domain_set_resources(device_t dev)
/* The following needs to be 2 lines, otherwise the second
* number is always 0
*/
- printk_info("Available memory: %dK", (uint32_t)tomk);
- printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
+ printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
+ printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
@@ -253,7 +253,7 @@ static void mc_read_resources(device_t dev)
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
- printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+ printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
}
@@ -289,15 +289,15 @@ static void northbridge_init(struct device *dev)
{
switch (pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
- printk_debug("Normal boot.\n");
+ printk(BIOS_DEBUG, "Normal boot.\n");
acpi_slp_type=0;
break;
case 0xcafed00d:
- printk_debug("S3 Resume.\n");
+ printk(BIOS_DEBUG, "S3 Resume.\n");
acpi_slp_type=3;
break;
default:
- printk_debug("Unknown boot method, assuming normal.\n");
+ printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
acpi_slp_type=0;
break;
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 3f73549eb6..444a360cd3 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -25,7 +25,7 @@
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...) printk_debug(x)
+#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
#endif
@@ -74,12 +74,12 @@ static void ram_read32(u32 offset)
static void sdram_dump_mchbar_registers(void)
{
int i;
- printk_debug("Dumping MCHBAR Registers\n");
+ printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
for (i=0; i<0xfff; i+=4) {
if (MCHBAR32(i) == 0)
continue;
- printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+ printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
}
}
#endif
@@ -94,7 +94,7 @@ static int memclk(void)
case 1: return 400;
case 2: return 533;
case 3: return 667;
- default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+ default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
}
return -1;
}
@@ -106,7 +106,7 @@ static int fsbclk(void)
case 0: return 400;
case 1: return 533;
case 3: return 667;
- default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+ default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return -1;
}
@@ -118,7 +118,7 @@ static int fsbclk(void)
case 0: return 1066;
case 1: return 533;
case 2: return 800;
- default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+ default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return -1;
}
@@ -234,7 +234,7 @@ static void sdram_detect_errors(void)
if (reg8 & ((1<<7)|(1<<2))) {
if (reg8 & (1<<2)) {
- printk_debug("SLP S4# Assertion Width Violation.\n");
+ printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
/* Write back clears bit 2 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
do_reset = 1;
@@ -242,7 +242,7 @@ static void sdram_detect_errors(void)
}
if (reg8 & (1<<7)) {
- printk_debug("DRAM initialization was interrupted.\n");
+ printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
reg8 &= ~(1<<7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
do_reset = 1;
@@ -254,7 +254,7 @@ static void sdram_detect_errors(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
if (do_reset) {
- printk_debug("Reset required.\n");
+ printk(BIOS_DEBUG, "Reset required.\n");
outb(0x00, 0xcf9);
outb(0x0e, 0xcf9);
for (;;) asm("hlt"); /* Wait for reset! */
@@ -300,10 +300,10 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
if (sdram_capabilities_dual_channel()) {
sysinfo->dual_channel = 1;
- printk_debug("This mainboard supports Dual Channel Operation.\n");
+ printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
} else {
sysinfo->dual_channel = 0;
- printk_debug("This mainboard supports only Single Channel Operation.\n");
+ printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
}
/**
@@ -339,10 +339,10 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
continue;
- printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
+ printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
- printk_debug("N/A\n");
+ printk(BIOS_DEBUG, "N/A\n");
continue;
}
@@ -360,29 +360,29 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
case 0x08:
switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
case 1:
- printk_debug("x8DDS\n");
+ printk(BIOS_DEBUG, "x8DDS\n");
sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
break;
case 0:
- printk_debug("x8DS\n");
+ printk(BIOS_DEBUG, "x8DS\n");
sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
break;
default:
- printk_debug ("Unsupported.\n");
+ printk(BIOS_DEBUG, "Unsupported.\n");
}
break;
case 0x10:
switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
case 1:
- printk_debug("x16DS\n");
+ printk(BIOS_DEBUG, "x16DS\n");
sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
break;
case 0:
- printk_debug("x16SS\n");
+ printk(BIOS_DEBUG, "x16SS\n");
sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
break;
default:
- printk_debug ("Unsupported.\n");
+ printk(BIOS_DEBUG, "Unsupported.\n");
}
break;
default:
@@ -397,7 +397,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
}
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- printk_info("Channel 0 has no memory populated.\n");
+ printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
}
}
@@ -556,7 +556,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
}
if (sysinfo->memory_frequency && sysinfo->cas) {
- printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
+ printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
sysinfo->memory_frequency, sysinfo->cas);
} else {
die("Could not find common memory frequency and CAS\n");
@@ -599,7 +599,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
die("DDR-II Module does not support this frequency (tRAS error)\n");
}
- printk_debug("tRAS = %d cycles\n", tRAS_cycles);
+ printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
sysinfo->tras = tRAS_cycles;
}
@@ -640,7 +640,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
die("DDR-II Module does not support this frequency (tRP error)\n");
}
- printk_debug("tRP = %d cycles\n", tRP_cycles);
+ printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
sysinfo->trp = tRP_cycles;
}
@@ -680,7 +680,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
die("DDR-II Module does not support this frequency (tRCD error)\n");
}
- printk_debug("tRCD = %d cycles\n", tRCD_cycles);
+ printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
sysinfo->trcd = tRCD_cycles;
}
@@ -720,7 +720,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
die("DDR-II Module does not support this frequency (tWR error)\n");
}
- printk_debug("tWR = %d cycles\n", tWR_cycles);
+ printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
sysinfo->twr = tWR_cycles;
}
@@ -756,7 +756,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
/* Can this happen? Go back to 127.5ns just to be sure
* we don't run out of the array. This may be wrong
*/
- printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
+ printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
reg8 = 3;
}
@@ -772,7 +772,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
}
sysinfo->trfc = tRFC_cycles[index];
- printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
+ printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
}
static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
@@ -804,7 +804,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
die("DDR-II module has unsupported refresh value\n");
}
- printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+ printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
}
static void sdram_verify_burst_length(struct sys_info * sysinfo)
@@ -1137,18 +1137,18 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
/* Dual Channel needs different tables. */
if (sdram_capabilities_dual_channel()) {
- printk_debug("Programming Dual Channel RCOMP\n");
+ printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
strength_multiplier = dual_channel_strength_multiplier;
dual_channel = 1;
idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2];
} else {
- printk_debug("Programming Single Channel RCOMP\n");
+ printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
strength_multiplier = single_channel_strength_multiplier;
dual_channel = 0;
idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
}
- printk_debug("Table Index: %d\n", idx);
+ printk(BIOS_DEBUG, "Table Index: %d\n", idx);
MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
@@ -1197,7 +1197,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
u32 chan0dll = 0, chan1dll = 0;
int i;
- printk_debug ("Programming DLL Timings... \n");
+ printk(BIOS_DEBUG, "Programming DLL Timings... \n");
MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1249,7 +1249,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
u8 reg8;
u32 reg32;
- printk_debug ("Initializing System Memory IO... \n");
+ printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
/* Enable Data Half Clock Pushout */
reg8 = MCHBAR8(C0HCTC);
reg8 &= ~0x1f;
@@ -1291,7 +1291,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
{
u32 reg32;
- printk_debug ("Enabling System Memory IO... \n");
+ printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
reg32 = MCHBAR32(RCVENMT);
reg32 &= ~(0x3f << 6);
@@ -1401,7 +1401,7 @@ static struct dimm_size sdram_get_dimm_size(u16 device)
/* Don't die here, I have not come across any of these to test what
* actually happens.
*/
- printk_err("Assymetric DIMMs are not supported by this chipset\n");
+ printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
sz.side2 -= (rows & 0x0f); /* Subtract out rows on side 1 */
sz.side2 += ((rows >> 4) & 0x0f); /* Add in rows on side 2 */
@@ -1445,7 +1445,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
- printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+ printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
if (!sz.side2)
continue;
@@ -1456,7 +1456,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
- printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
+ printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
}
}
@@ -1465,7 +1465,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
int i;
int cum0, cum1, tolud, tom;
- printk_debug ("Setting RAM size... \n");
+ printk(BIOS_DEBUG, "Setting RAM size... \n");
cum0 = 0;
for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1507,9 +1507,9 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
- printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
- printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
- printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+ printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
+ printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
+ printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
@@ -1521,7 +1521,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
int i, value;
u16 dra0=0, dra1=0, dra = 0;
- printk_debug ("Setting row attributes... \n");
+ printk(BIOS_DEBUG, "Setting row attributes... \n");
for(i=0; i < 2 * DIMM_SOCKETS; i++) {
u16 device;
u8 columnsrows;
@@ -1561,8 +1561,8 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
MCHBAR16(C0DRA0) = dra0;
MCHBAR16(C1DRA0) = dra1;
- printk_debug("C0DRA = 0x%04x\n", dra0);
- printk_debug("C1DRA = 0x%04x\n", dra1);
+ printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
+ printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
return 0;
}
@@ -1587,7 +1587,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
if (sysinfo->banks[i] != 8)
continue;
- printk_spew("DIMM%d has 8 banks.\n", i);
+ printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
if (i & 1)
MCHBAR16(off32) |= 0x50;
@@ -1852,7 +1852,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
{
u32 reg32;
- printk_debug("Setting mode of operation for memory channels...");
+ printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
if (sdram_capabilities_interleave() &&
( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
@@ -1870,21 +1870,21 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
if(sysinfo->interleaved) {
/* Dual Channel Interleaved */
- printk_debug("Dual Channel Interleaved.\n");
+ printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
reg32 |= (1 << 1);
} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
/* Channel 1 only */
- printk_debug("Single Channel 1 only.\n");
+ printk(BIOS_DEBUG, "Single Channel 1 only.\n");
reg32 |= (1 << 2);
} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
SYSINFO_DIMM_NOT_POPULATED) {
/* Dual Channel Assymetric */
- printk_debug("Dual Channel Assymetric.\n");
+ printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
reg32 |= (1 << 0);
} else {
/* All bits 0 means Single Channel 0 operation */
- printk_debug("Single Channel 0 only.\n");
+ printk(BIOS_DEBUG, "Single Channel 0 only.\n");
}
reg32 |= (1 << 10);
@@ -1934,14 +1934,14 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
#define VOLTAGE_1_05 0x00
#define VOLTAGE_1_50 0x01
- printk_debug ("Setting Graphics Frequency... \n");
+ printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
- printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
+ printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
voltage = VOLTAGE_1_05;
if (MCHBAR32(DFT_STRAP1) & (1 << 20))
voltage = VOLTAGE_1_50;
- printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
+ printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
/* Gate graphics hardware for frequency change */
reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
@@ -1971,12 +1971,12 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
freq = CRCLK_166MHz;
}
- printk_debug("Render: ");
+ printk(BIOS_DEBUG, "Render: ");
switch (freq) {
- case CRCLK_166MHz: printk_debug("166Mhz"); break;
- case CRCLK_200MHz: printk_debug("200Mhz"); break;
- case CRCLK_250MHz: printk_debug("250Mhz"); break;
- case CRCLK_400MHz: printk_debug("400Mhz"); break;
+ case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
+ case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
+ case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
+ case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
}
if (i945_silicon_revision() == 0) {
@@ -2021,10 +2021,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
if (voltage == VOLTAGE_1_05) {
reg8 |= CDCLK_200MHz;
- printk_debug(" Display: 200MHz\n");
+ printk(BIOS_DEBUG, " Display: 200MHz\n");
} else {
reg8 |= CDCLK_320MHz;
- printk_debug(" Display: 320MHz\n");
+ printk(BIOS_DEBUG, " Display: 320MHz\n");
}
pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
@@ -2050,21 +2050,21 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
offset++;
#endif
- printk_debug ("Setting Memory Frequency... ");
+ printk(BIOS_DEBUG, "Setting Memory Frequency... ");
clkcfg = MCHBAR32(CLKCFG);
- printk_debug("CLKCFG=0x%08x, ", clkcfg);
+ printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
if (sysinfo->mvco4x) {
- printk_debug("MVCO 4x, ");
+ printk(BIOS_DEBUG, "MVCO 4x, ");
clkcfg &= ~(1 << 12);
}
if (sysinfo->clkcfg_bit7) {
- printk_debug("second VCO, ");
+ printk(BIOS_DEBUG, "second VCO, ");
clkcfg |= (1 << 7);
}
@@ -2077,7 +2077,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
}
if (MCHBAR32(CLKCFG) == clkcfg) {
- printk_debug ("ok (unchanged)\n");
+ printk(BIOS_DEBUG, "ok (unchanged)\n");
return;
}
@@ -2118,8 +2118,8 @@ cache_code:
goto vco_update;
out:
- printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
- printk_debug ("ok\n");
+ printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
+ printk(BIOS_DEBUG, "ok\n");
}
static void sdram_program_clock_crossing(void)
@@ -2222,28 +2222,28 @@ static void sdram_program_clock_crossing(void)
};
#endif
- printk_debug("Programming Clock Crossing...");
+ printk(BIOS_DEBUG, "Programming Clock Crossing...");
- printk_debug("MEM=");
+ printk(BIOS_DEBUG, "MEM=");
switch (memclk()) {
- case 400: printk_debug("400"); idx += 0; break;
- case 533: printk_debug("533"); idx += 2; break;
- case 667: printk_debug("667"); idx += 4; break;
- default: printk_debug("RSVD %x", memclk()); return;
+ case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
+ case 533: printk(BIOS_DEBUG, "533"); idx += 2; break;
+ case 667: printk(BIOS_DEBUG, "667"); idx += 4; break;
+ default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
}
- printk_debug(" FSB=");
+ printk(BIOS_DEBUG, " FSB=");
switch (fsbclk()) {
- case 400: printk_debug("400"); idx += 0; break;
- case 533: printk_debug("533"); idx += 6; break;
- case 667: printk_debug("667"); idx += 12; break;
- case 800: printk_debug("800"); idx += 18; break;
- case 1066: printk_debug("1066"); idx += 24; break;
- default: printk_debug("RSVD %x\n", fsbclk()); return;
+ case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
+ case 533: printk(BIOS_DEBUG, "533"); idx += 6; break;
+ case 667: printk(BIOS_DEBUG, "667"); idx += 12; break;
+ case 800: printk(BIOS_DEBUG, "800"); idx += 18; break;
+ case 1066: printk(BIOS_DEBUG, "1066"); idx += 24; break;
+ default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
}
if (command_clock_crossing[idx]==0xffffffff) {
- printk_debug("Invalid MEM/FSB combination!\n");
+ printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
}
MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
@@ -2254,7 +2254,7 @@ static void sdram_program_clock_crossing(void)
MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
- printk_debug("... ok\n");
+ printk(BIOS_DEBUG, "... ok\n");
}
static void sdram_disable_fast_dispatch(void)
@@ -2569,7 +2569,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
#ifdef C2_SELF_REFRESH_DISABLE
if (integrated_graphics) {
- printk_debug("C2 self-refresh with IGD\n");
+ printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
MCHBAR16(MIPMC4) = 0x0468;
MCHBAR16(MIPMC5) = 0x046c;
MCHBAR16(MIPMC6) = 0x046c;
@@ -2728,7 +2728,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
- printk_debug("one dimm per channel config.. \n");
+ printk(BIOS_DEBUG, "one dimm per channel config.. \n");
reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28);
@@ -2832,7 +2832,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
continue;
}
- printk_debug("jedec enable sequence: bank %d\n", i);
+ printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
switch (i) {
case 0:
/* Start at address 0 */
@@ -2845,7 +2845,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
}
default:
if (nonzero != -1) {
- printk_debug("bankaddr from bank size of rank %d\n", nonzero);
+ printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
bankaddr += sysinfo->banksize[nonzero] <<
(sysinfo->interleaved ? 26 : 25);
break;
@@ -3010,7 +3010,7 @@ void sdram_initialize(int boot_path)
sdram_detect_errors();
- printk_debug ("Setting up RAM controller.\n");
+ printk(BIOS_DEBUG, "Setting up RAM controller.\n");
memset(&sysinfo, 0, sizeof(sysinfo));
@@ -3131,7 +3131,7 @@ void sdram_initialize(int boot_path)
reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
- printk_debug("RAM initialization finished.\n");
+ printk(BIOS_DEBUG, "RAM initialization finished.\n");
sdram_setup_processor_side();
}
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 846af4f080..a912b2695f 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -67,7 +67,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
{
u32 reg32;
- printk_spew(" set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
+ printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
reg32 = MCHBAR32(C0DRT1 + channel_offset);
reg32 &= 0xf0ffffff;
@@ -76,7 +76,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
/* This should never happen: */
if (coarse > 0x0f)
- printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
+ printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
/* medium control
*
@@ -102,7 +102,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
{
- printk_spew(" normalize()\n");
+ printk(BIOS_SPEW, " normalize()\n");
if (*fine < 0x80)
return 0;
@@ -111,7 +111,7 @@ static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
*mediumcoarse += 1;
if (*mediumcoarse >= 0x40) {
- printk_debug("Normalize Error\n");
+ printk(BIOS_DEBUG, "Normalize Error\n");
return -1;
}
@@ -129,11 +129,11 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
/* find start of the data phase */
u32 reg32;
- printk_spew(" find_preamble()\n");
+ printk(BIOS_SPEW, " find_preamble()\n");
do {
if (*mediumcoarse < 4) {
- printk_debug("No Preamble found.\n");
+ printk(BIOS_DEBUG, "No Preamble found.\n");
return -1;
}
*mediumcoarse -= 4;
@@ -146,7 +146,7 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
} while (reg32 & (1 << 19));
if (!(reg32 & (1 << 18))) {
- printk_debug("No Preamble found (neither high nor low).\n");
+ printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n");
return -1;
}
@@ -159,14 +159,14 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
{
- printk_spew(" add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
+ printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
*mediumcoarse, *fine);
if (*fine >= 0x80) {
*fine -= 0x80;
*mediumcoarse += 2;
if (*mediumcoarse >= 0x40) {
- printk_debug("clocks at max.\n");
+ printk(BIOS_DEBUG, "clocks at max.\n");
return -1;
}
@@ -186,7 +186,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
{
u32 rcvenmt;
- printk_spew(" find_strobes_low()\n");
+ printk(BIOS_SPEW, " find_strobes_low()\n");
for (;;) {
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -211,7 +211,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
}
- printk_debug("Could not find low strobe\n");
+ printk(BIOS_DEBUG, "Could not find low strobe\n");
return 0;
}
@@ -222,7 +222,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
int counter;
u32 rcvenmt;
- printk_spew(" find_strobes_edge()\n");
+ printk(BIOS_SPEW, " find_strobes_edge()\n");
counter = 8;
set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -257,7 +257,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
continue;
}
- printk_debug("Could not find rising edge.\n");
+ printk(BIOS_DEBUG, "Could not find rising edge.\n");
return -1;
}
@@ -286,7 +286,7 @@ static int receive_enable_autoconfig(int channel_offset,
u8 mediumcoarse;
u8 fine;
- printk_spew("receive_enable_autoconfig() for channel %d\n",
+ printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
channel_offset ? 1 : 0);
/* Set initial values */
@@ -315,7 +315,7 @@ static int receive_enable_autoconfig(int channel_offset,
* It can be removed when the output message is not printed anymore
*/
if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
- printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
+ printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
}
return 0;