diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-15 15:34:24 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:30:00 +0200 |
| commit | b91a0f2b83ac7816dc28cac8d3ae13a7d5576864 (patch) | |
| tree | 02b0647a20ac1ae02970d1e67fee9a1e1b4534e5 /src/northbridge/intel | |
| parent | 9764d4c690bbe4a54429e47a2094230da5fb88f5 (diff) | |
Rename cache_lbmem() to cache_ramstage()
... and don't require it to specify a cache type.
This function is only used on romcc boards, and should go away
(because all boards should be switched to CAR)
Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/e7520/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/e7525/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index d226085d0d..191c077803 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -1334,5 +1334,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index b5895bc647..c491a7ed2d 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -1307,5 +1307,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 050df951e5..b453e8ba87 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1198,6 +1198,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* The memory is now setup, use it */ #if !CONFIG_CACHE_AS_RAM - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); #endif } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 79fc5f72e2..5fe206ff2a 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -772,7 +772,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } static inline int memory_initialized(void) |