nb/intel/gm45: Add more DMIBAR/EPBAR registers

Add definitions for more DMIBAR/EPBAR registers, and specify their sizes
as well. Also, expand a comment as the registers' purpose is now known.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 78 insertions, 43 deletions

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 95457fb4b7..0fec20c1f2 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -359,14 +359,29 @@ enum {
 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
 
-#define DMIVC0RCTL	0x14
-#define DMIVC1RCTL	0x20
-#define DMIVC1RSTS	0x26
-#define DMIESD		0x44
-#define DMILE1D		0x50
-#define DMILE1A		0x58
-#define DMILE2D		0x60
-#define DMILE2A		0x68
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+#define  VC0NP		(1 << 1)
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+#define  VC1NP		(1 << 1)
+
+#define DMIESD		0x044	/* 32bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
 
 /*
  * EPBAR
@@ -376,10 +391,30 @@ enum {
 #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
 #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
 
-#define EPESD		0x44
-#define EPLE1D		0x50
-#define EPLE1A		0x58
-#define EPLE2D		0x60
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCTL	0x00c	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPVC1MTS	0x028	/* 32bit */
+#define EPVC1ITC	0x02c	/* 32bit */
+
+#define EPVC1IST	0x038	/* 64bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#define EP_PORTARB(x)	(0x100 + 4 * (x))	/* 256bit */
 
 #ifndef __ACPI__
 
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 0eb1287f3b..ce49d6200d 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -10,34 +10,34 @@
 static void init_egress(void)
 {
 	/* VC0: TC0 only */
-	EPBAR8(0x14) &= 1;
-	EPBAR8(0x4) = (EPBAR8(0x4) & ~7) | 1;
+	EPBAR8(EPVC0RCTL) &= 1;
+	EPBAR8(EPPVCCAP1) = (EPBAR8(EPPVCCAP1) & ~7) | 1;
 
 	/* VC1: isoch */
-	EPBAR32(0x28) = 0x0a0a0a0a;
-	EPBAR32(0x1c) = (EPBAR32(0x1c) & ~(127 << 16)) | (0x0a << 16);
+	EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
+	EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~(127 << 16)) | (0x0a << 16);
 
 	/* VC1: ID1, TC7 */
-	EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
-	EPBAR8(0x20) = (EPBAR8(0x20) & 1) | (1 << 7);
+	EPBAR32(EPVC1RCTL) = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
+	EPBAR8(EPVC1RCTL) = (EPBAR8(EPVC1RCTL) & 1) | (1 << 7);
 
 	/* VC1 ARB table: setup and enable */
-	EPBAR32(0x100) = 0x55555555;
-	EPBAR32(0x104) = 0x55555555;
-	EPBAR32(0x108) = 0x55555555;
-	EPBAR32(0x10c) = 0x55555555;
-	EPBAR32(0x110) = 0x55555555;
-	EPBAR32(0x114) = 0x55555555;
-	EPBAR32(0x118) = 0x55555555;
-	EPBAR32(0x11c) = 0x00005555;
-	EPBAR32(0x20) |= 1 << 16;
-
-	while ((EPBAR8(0x26) & 1) != 0);
+	EPBAR32(EP_PORTARB(0)) = 0x55555555;
+	EPBAR32(EP_PORTARB(1)) = 0x55555555;
+	EPBAR32(EP_PORTARB(2)) = 0x55555555;
+	EPBAR32(EP_PORTARB(3)) = 0x55555555;
+	EPBAR32(EP_PORTARB(4)) = 0x55555555;
+	EPBAR32(EP_PORTARB(5)) = 0x55555555;
+	EPBAR32(EP_PORTARB(6)) = 0x55555555;
+	EPBAR32(EP_PORTARB(7)) = 0x00005555;
+	EPBAR32(EPVC1RCTL) |= 1 << 16;
+
+	while ((EPBAR8(EPVC1RSTS) & 1) != 0);
 
 	/* VC1: enable */
-	EPBAR32(0x20) |= 1 << 31;
+	EPBAR32(EPVC1RCTL) |= 1 << 31;
 
-	while ((EPBAR8(0x26) & 2) != 0);
+	while ((EPBAR8(EPVC1RSTS) & 2) != 0);
 }
 
 /* MCH side */
@@ -46,16 +46,16 @@ static void init_dmi(int b2step)
 {
 	/* VC0: TC0 only */
 	DMIBAR8(DMIVC0RCTL) &= 1;
-	DMIBAR8(0x4) = (DMIBAR8(0x4) & ~7) | 1;
+	DMIBAR8(DMIPVCCAP1) = (DMIBAR8(DMIPVCCAP1) & ~7) | 1;
 
 	/* VC1: ID1, TC7 */
-	DMIBAR32(0x20) = (DMIBAR32(0x20) & ~(7 << 24)) | (1 << 24);
-	DMIBAR8(0x20) = (DMIBAR8(0x20) & 1) | (1 << 7);
+	DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
+	DMIBAR8(DMIVC1RCTL) = (DMIBAR8(DMIVC1RCTL) & 1) | (1 << 7);
 
 	/* VC1: enable */
-	DMIBAR32(0x20) |= 1 << 31;
+	DMIBAR32(DMIVC1RCTL) |= 1 << 31;
 
-	while ((DMIBAR8(0x26) & 2) != 0);
+	while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0);
 
 	/* additional configuration. */
 	DMIBAR32(0x200) |= 3 << 13;
@@ -223,11 +223,11 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
 	   the endpoint (ICH), but ICH doesn't give any limits. */
 
 	if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0)))
-		DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once)
+		DMIBAR8(DMILCTL) |= (3 << 0); // enable ASPM L0s, L1 (write-once)
 	else
-		DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once)
+		DMIBAR8(DMILCTL) |= (1 << 0); // enable ASPM L0s (write-once)
 	/* timing */
-	DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15);
+	DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~(63 << 12)) | (2 << 12) | (2 << 15);
 	DMIBAR8(0x208 + 3) = 0;
 	DMIBAR32(0x208) &= ~(3 << 20);
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 7fc97f01a1..f9d7c8fbed 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1128,7 +1128,7 @@ static void clock_crossing_setup(const fsb_clock_t fsb,
 	}
 }
 
-/* Program egress VC1 timings. */
+/* Program egress VC1 isoch timings. */
 static void vc1_program_timings(const fsb_clock_t fsb)
 {
 	const u32 timings_by_fsb[][2] = {
@@ -1136,9 +1136,9 @@ static void vc1_program_timings(const fsb_clock_t fsb)
 	/* FSB  800MHz */ { 0x14, 0x00f000f0 },
 	/* FSB  667MHz */ { 0x10, 0x00c000c0 },
 	};
-	EPBAR8(0x2c)  = timings_by_fsb[fsb][0];
-	EPBAR32(0x38) = timings_by_fsb[fsb][1];
-	EPBAR32(0x3c) = timings_by_fsb[fsb][1];
+	EPBAR8(EPVC1ITC)      = timings_by_fsb[fsb][0];
+	EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1];
+	EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1];
 }
 
 #define DEFAULT_PCI_MMIO_SIZE 2048