diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-07 00:03:33 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-18 20:49:46 +0100 |
| commit | 38d9423dbe300514e1ba7224a962650980a96217 (patch) | |
| tree | 6852430fd98517b90cc91188b22c52cb20b9c66e /src/northbridge/intel | |
| parent | a267161362f23b94f2e7677a8ea55f729578a049 (diff) | |
haswell: romstage: pass stack pointer and MTRRs
Instead of hard coding the policy for the stack and MTRR values after
the cache-as-ram is torn down, allow for the C code to pass those
policies back to the cache-as-ram assembly file. That way, ramstage
relocation can use a different stack as well as different MTRR policies.
Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2755
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions