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authorAaron Durbin <adurbin@chromium.org>2013-02-27 22:50:12 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-22 00:13:42 +0100
commitdd4a6d2357decf0cf505370234b378985c68f97f (patch)
tree6c656e9d13fbc39a9a88766d9b3f533a98a9f89b /src/northbridge/intel
parent24d1d4b47274eb82893e6726472a991a36fce0aa (diff)
coreboot: dynamic cbmem requirement
Dynamic cbmem is now a requirement for relocatable ramstage. This patch replaces the reserve_* fields in the romstage_handoff structure by using the dynamic cbmem library. The haswell code is not moved over in this commit, but it should be safe because there is a hard requirement for DYNAMIC_CBMEM when using a reloctable ramstage. Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/northbridge.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 87081385b5..53c2f366c2 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -543,21 +543,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-#if CONFIG_EARLY_CBMEM_INIT
-int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size)
-{
- uint32_t tseg;
-
- /* Put the CBMEM location just below TSEG. */
- *tables_size = HIGH_MEMORY_SIZE;
- tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
- TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE;
- *tables_base = tseg;
-
- return 0;
-}
-#endif
-
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME