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authorAngel Pons <th3fanbus@gmail.com>2021-01-12 23:38:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-15 11:20:18 +0000
commitbc15e0195832e40b37df9fd6e658659e2982cfbd (patch)
tree591e6a7a464ba3421adc68c6190358da4c0f98d7 /src/northbridge/intel
parenteef4343a9f0e94a5a2137793d15c582278715d28 (diff)
nb/intel/x4x: Reset DQS probe on all channels
Eaglelake MRC 2.55 does this, and also stalls for less time. Change-Id: Iaaefd32c341a490e5c129df865407ec3f8da8212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/x4x/rcven.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 8a86ce9cb5..1f49beb61c 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -28,11 +28,13 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel)
{
u32 sample_offset = 0x400 * channel + 0x561 + lane * 4;
- /* Reset the DQS probe */
- MCHBAR8(RESET_CNTL(channel)) &= ~0x2;
- udelay(2);
- MCHBAR8(RESET_CNTL(channel)) |= 0x2;
- udelay(2);
+ /* Reset the DQS probe, on both channels? */
+ for (u8 i = 0; i < TOTAL_CHANNELS; i++) {
+ MCHBAR8(RESET_CNTL(i)) &= ~0x2;
+ udelay(1);
+ MCHBAR8(RESET_CNTL(i)) |= 0x2;
+ udelay(1);
+ }
mfence();
/* Read strobe */
read32((u32 *)addr);