diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-31 08:27:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:58:56 +0000 |
| commit | b96c3587517448498412ac7b31bf9af405a3c518 (patch) | |
| tree | 41ca9856014c496f185843dd7e9981be67f6f3bd /src/northbridge/intel | |
| parent | 9cbf26d18e0263c964dd8faf7bc04d7dbb468337 (diff) | |
nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.
Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/bootblock.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 64e2258c46..0bb8ae2aad 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "haswell.h" static uint32_t encode_pciexbar_length(void) @@ -28,7 +29,7 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } |