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authorChristian Gmeiner <christian.gmeiner@gmail.com>2013-03-12 11:07:07 +0100
committerMarc Jones <marc.jones@se-eng.com>2013-03-14 16:32:45 +0100
commit4412bc4ae8f8ab33a49cdd00098754ff7c333a01 (patch)
tree508e5abc7e9347d01840bbaf642fa14ce177812a /src/northbridge/intel
parent138f2cede491b65cfd8c73b9185a2dc7ee10b8b3 (diff)
OT200: reset MFGTP7 (backlight pwm)
The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2527 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/northbridge/intel')
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