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authorMyles Watson <mylesgw@gmail.com>2009-07-02 18:56:24 +0000
committerMyles Watson <mylesgw@gmail.com>2009-07-02 18:56:24 +0000
commit29cc9eda2021a87396ef31a6fc81daff6fd1be7a (patch)
treed3dfa07ca85547c77c5d07825fc8afcc19489076 /src/northbridge/intel
parent2468331952bae0abdc4d76dbe6cf26f05b7825e5 (diff)
Move the v3 resource allocator to v2.
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7501/northbridge.c23
-rw-r--r--src/northbridge/intel/e7520/northbridge.c41
-rw-r--r--src/northbridge/intel/e7525/northbridge.c43
-rw-r--r--src/northbridge/intel/i3100/northbridge.c35
-rw-r--r--src/northbridge/intel/i440bx/northbridge.c28
-rw-r--r--src/northbridge/intel/i82810/northbridge.c27
-rw-r--r--src/northbridge/intel/i82830/northbridge.c25
-rw-r--r--src/northbridge/intel/i855gme/northbridge.c24
-rw-r--r--src/northbridge/intel/i855pm/northbridge.c23
-rw-r--r--src/northbridge/intel/i945/northbridge.c32
10 files changed, 22 insertions, 279 deletions
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 06a68e1e47..ee5f62f328 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -9,23 +9,6 @@
#include <bitops.h>
#include "chip.h"
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- unsigned reg;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0x400; //yhlu
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -155,12 +138,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index 47e6266aa6..da3d71b91f 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -28,30 +28,6 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
@@ -90,7 +66,7 @@ static void pci_domain_set_resources(device_t dev)
#if 1
printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif
+#endif
/* FIXME Me temporary hack */
if(pci_tolm > 0xe0000000)
pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@ static void pci_domain_set_resources(device_t dev)
remapbasek = 0x3ff << 16;
remaplimitk = 0 << 16;
remapoffsetk = 0 << 16;
- }
+ }
else {
/* The PCI memory hole overlaps memory
* setup the remap window.
@@ -165,7 +141,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
}
if (remaplimitk >= remapbasek) {
- ram_resource(dev, 6, remapbasek,
+ ram_resource(dev, 6, remapbasek,
(remaplimitk + 64*1024) - remapbasek);
}
@@ -178,13 +154,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7520_domain_scan_bus(device_t dev, u32 max)
{
- max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
- if (max > max_bus) {
- max_bus = max;
- }
- return max;
+ max_bus = pci_domain_scan_bus(dev, max);
+ return max_bus;
}
static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
- .scan_bus = pci_domain_scan_bus,
+ .scan_bus = e7520_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
};
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 65404d6bf3..1963a0d83e 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -28,30 +28,6 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
@@ -90,7 +66,7 @@ static void pci_domain_set_resources(device_t dev)
#if 1
printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif
+#endif
/* FIXME Me temporary hack */
if(pci_tolm > 0xe0000000)
pci_tolm = 0xe0000000;
@@ -122,7 +98,7 @@ static void pci_domain_set_resources(device_t dev)
remapbasek = 0x3ff << 16;
remaplimitk = 0 << 16;
remapoffsetk = 0 << 16;
- }
+ }
else {
/* The PCI memory hole overlaps memory
* setup the remap window.
@@ -160,12 +136,12 @@ static void pci_domain_set_resources(device_t dev)
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
- ram_resource(dev, 4, 768, tolmk - 768);
+ ram_resource(dev, 4, 768, (tolmk - 768));
if (tomk > 4*1024*1024) {
ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
}
if (remaplimitk >= remapbasek) {
- ram_resource(dev, 6, remapbasek,
+ ram_resource(dev, 6, remapbasek,
(remaplimitk + 64*1024) - remapbasek);
}
@@ -178,13 +154,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7525_domain_scan_bus(device_t dev, u32 max)
{
- max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
- if (max > max_bus) {
- max_bus = max;
- }
- return max;
+ max_bus = pci_domain_scan_bus(dev, max);
+ return max_bus;
}
static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
- .scan_bus = pci_domain_scan_bus,
+ .scan_bus = e7525_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
};
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 205e47db50..c96dcee8ba 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -49,30 +49,6 @@ static void ram_resource(device_t dev, u32 index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
@@ -199,13 +175,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static u32 pci_domain_scan_bus(device_t dev, u32 max)
+static u32 i3100_domain_scan_bus(device_t dev, u32 max)
{
- max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
- if (max > max_bus) {
- max_bus = max;
- }
- return max;
+ max_bus = pci_domain_scan_bus(dev, max);
+ return max_bus;
}
static struct device_operations pci_domain_ops = {
@@ -213,7 +186,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
- .scan_bus = pci_domain_scan_bus,
+ .scan_bus = i3100_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
};
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 34c868e0f3..05c614cb7a 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -33,24 +33,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7190,
};
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -95,7 +77,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
extern uint64_t high_tables_base, high_tables_size;
#endif
-static void pci_domain_set_resources(device_t dev)
+static void i440bx_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
@@ -140,15 +122,9 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
+ .set_resources = i440bx_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 4b3c321963..c705b55a45 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -52,27 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7120,
};
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- unsigned reg;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -181,12 +160,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index 9f6ba71d41..2b913ea287 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -51,25 +51,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
.device = 0x3575,
};
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide I/O space constraints. */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints. */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -158,12 +139,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
diff --git a/src/northbridge/intel/i855gme/northbridge.c b/src/northbridge/intel/i855gme/northbridge.c
index ad48ee11de..5ad2122d37 100644
--- a/src/northbridge/intel/i855gme/northbridge.c
+++ b/src/northbridge/intel/i855gme/northbridge.c
@@ -31,24 +31,6 @@
#include <cpu/x86/cache.h>
#include "chip.h"
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- unsigned reg;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -156,12 +138,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index ce655a9f0d..f6a23914e2 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -10,23 +10,6 @@
#include <bitops.h>
#include "chip.h"
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -123,12 +106,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index b0ddbda7e4..c07a00c149 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -43,31 +43,6 @@ static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->base = 0;
- resource->size = 0;
- resource->align = 0;
- resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
@@ -184,15 +159,10 @@ static void pci_domain_set_resources(device_t dev)
#endif
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
+ * See e7525/northbridge.c for an example.
*/
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,