summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2016-03-15 09:05:54 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-16 18:55:51 +0100
commit264bf0b27e6202dfca27c285c9dde10d08b8f023 (patch)
tree6ce70301f75bfaff39e95b2b17130aa9935a4d02 /src/northbridge/intel
parent94534b31328311e3a3488a7f8201bc0abab9fb1d (diff)
cpu/x86/mtrr: move cache_ramstage() to its only user
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i3100/raminit.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b426cb8043..53bf17c8d2 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -926,6 +926,13 @@ static void set_receive_enable(const struct mem_controller *ctrl)
write32(MCBAR+0x154, recenb);
}
+static void cache_ramstage(void)
+{
+ /* Enable caching for lower 1MB and ram stage using variable mtrr */
+ disable_cache();
+ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+ enable_cache();
+}
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
@@ -1189,7 +1196,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if !CONFIG_CACHE_AS_RAM
- cache_ramstage();
-#endif
+ if (!IS_ENABLED(CONFIG_CACHE_AS_RAM))
+ cache_ramstage();
}