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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-17 18:10:49 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-23 02:35:53 +0000 |
| commit | 4ce0a07f0670e74dd22d5f7af4b8603db2320ded (patch) | |
| tree | 60679c42a7f8eba961dab8c8d9fcdfb14b02c47b /src/northbridge/intel/x4x | |
| parent | b6fc13b3dbc943b4981b6b33ba7a0e025c62398a (diff) | |
nb/intel/x4x,sandybridge: Move romstage_handoff_init() call
Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/romstage.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 2 |
3 files changed, 6 insertions, 11 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index ea41e76dce..f942d59758 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -10,7 +10,6 @@ #include <option.h> #include "x4x.h" #include <console/console.h> -#include <romstage_handoff.h> void x4x_early_init(void) { @@ -216,14 +215,8 @@ static void init_dmi(void) DMIBAR16(DMILCTL); } -static void x4x_prepare_resume(int s3resume) -{ - romstage_handoff_init(s3resume); -} - -void x4x_late_init(int s3resume) +void x4x_late_init(void) { init_egress(); init_dmi(); - x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 648520c038..c70c1fb46c 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> +#include <romstage_handoff.h> #include <southbridge/intel/common/pmclib.h> #include <arch/romstage.h> @@ -42,7 +43,8 @@ void mainboard_romstage_entry(void) mb_get_spd_map(spd_addr_map); sdram_initialize(boot_path, spd_addr_map); - x4x_late_init(s3_resume); - + x4x_late_init(); printk(BIOS_DEBUG, "x4x late init complete\n"); + + romstage_handoff_init(s3_resume); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index b5842eef0d..c1177f05ef 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -157,7 +157,7 @@ #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ void x4x_early_init(void); -void x4x_late_init(int s3resume); +void x4x_late_init(void); void mb_get_spd_map(u8 spd_map[4]); void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); |