diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-08-31 17:09:28 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-20 14:24:57 +0000 |
| commit | 0b0113f2436b448cd172d2ae9cfcc07628020173 (patch) | |
| tree | 627b1a81d647e9084763dd18eaca22022bd4568c /src/northbridge/intel/x4x | |
| parent | ce84a347bfa16f393e75e4cc63eded636ca69af8 (diff) | |
device/device.h: Rename pci_domain_scan_bus
On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index a3e1bd29d8..12a7a40d06 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -111,7 +111,7 @@ struct device_operations x4x_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt = generate_cpu_entries, .acpi_name = northbridge_acpi_name, |