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authorNico Huber <nico.h@gmx.de>2020-04-26 17:01:25 +0200
committerNico Huber <nico.h@gmx.de>2020-05-27 21:34:49 +0000
commitf2a0be235cdf72caff549a1cfe0b986bdd99e93b (patch)
treed2e66798375f6b644c97206d65684b9f7e95ce9d /src/northbridge/intel/x4x
parent4dc4cb6b5c835ca947356a4d4e8c10228966bebc (diff)
drivers/intel/gma: Move IGD OpRegion to CBMEM
It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
-rw-r--r--src/northbridge/intel/x4x/gma.c51
1 files changed, 2 insertions, 49 deletions
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 0067d71bbc..004960fd8c 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -6,7 +6,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
-#include <cbmem.h>
#include <drivers/intel/gma/intel_bios.h>
#include <drivers/intel/gma/edid.h>
#include <drivers/intel/gma/i915.h>
@@ -19,31 +18,14 @@
#include "drivers/intel/gma/i915_reg.h"
#include "x4x.h"
-#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
-#include <southbridge/intel/i82801jx/nvs.h>
-#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
-#include <southbridge/intel/i82801gx/nvs.h>
-#endif
-
#define BASE_FREQUENCY 96000
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
- const global_nvs_t *gnvs_ptr = gnvs;
- return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
- global_nvs_t *gnvs_ptr = gnvs;
- if (gnvs_ptr)
- gnvs_ptr->aslb = aslb;
-}
-
static void gma_func0_init(struct device *dev)
{
u32 reg32;
+ intel_gma_init_igd_opregion();
+
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
@@ -65,8 +47,6 @@ static void gma_func0_init(struct device *dev)
} else {
pci_dev_init(dev);
}
-
- intel_gma_restore_opregion();
}
static void gma_func0_disable(struct device *dev)
@@ -86,32 +66,6 @@ static void gma_generate_ssdt(const struct device *device)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
-static unsigned long
-gma_write_acpi_tables(const struct device *const dev,
- unsigned long current,
- struct acpi_rsdp *const rsdp)
-{
- igd_opregion_t *opregion = (igd_opregion_t *)current;
- global_nvs_t *gnvs;
-
- if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
- return current;
-
- current += sizeof(igd_opregion_t);
-
- /* GNVS has been already set up */
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (gnvs) {
- /* IGD OpRegion Base Address */
- gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
- } else {
- printk(BIOS_ERR, "Error: GNVS table not found.\n");
- }
-
- current = acpi_align_current(current);
- return current;
-}
-
static const char *gma_acpi_name(const struct device *dev)
{
return "GFX0";
@@ -130,7 +84,6 @@ static struct device_operations gma_func0_ops = {
.ops_pci = &gma_pci_ops,
.disable = gma_func0_disable,
.acpi_name = gma_acpi_name,
- .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = {