diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 06:25:55 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-28 22:51:27 +0000 |
| commit | d53fd704f252ffde35c8bf2f2b16260edce76e79 (patch) | |
| tree | af78a8f39e05c14375cd773699e7532ac410ca20 /src/northbridge/intel/x4x | |
| parent | b371e233eb96daaa4b5ee3a75ef78068524210fb (diff) | |
intel/smm/gen1: Use smm_subregion()
Change-Id: I371ed41f485b3143e47f091681198d6674928897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/memmap.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 2f50768c46..41e491200b 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -25,10 +25,10 @@ #include <device/pci_def.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> #include <cpu/intel/smm_reloc.h> -#include <stage_cache.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -112,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len) return 1; } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); return decode_tseg_size(esmramc); } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); } @@ -134,14 +134,10 @@ void *cbmem_top(void) return (void *) top_of_ram; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) |