nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK

There is some overlap between things done in bootblock
and romstage like setting BARs.

Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 6 insertions, 20 deletions

diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 8f002c6a8f..2a54e2495e 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_GMA_ACPI
 	select CACHE_MRC_SETTINGS
 	select PARALLEL_MP
+	select C_ENVIRONMENT_BOOTBLOCK
 
 config CBFS_SIZE
 	hex
 	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
-	default "northbridge/intel/x4x/bootblock.c"
-
 config VGA_BIOS_ID
 	string
 	default "8086,2e32"
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 79a03cb77e..cde7121f93 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -16,6 +16,8 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
 
+bootblock-y += bootblock.c
+
 romstage-y += early_init.c
 romstage-y += raminit.c
 romstage-y += raminit_ddr23.c
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index e733287e93..64643dd79c 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -15,13 +15,11 @@
  */
 
 #include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "x4x.h"
 #include "iomap.h"
 
-/* Just re-define these instead of including x4x.h. It blows up romcc. */
-#define D0F0_PCIEXBAR_LO 0x60
-#define D0F0_PCIEXBAR_HI 0x64
-
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
 {
 	uint32_t reg32;
 
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c
index c3a503643f..eae87f3674 100644
--- a/src/northbridge/intel/x4x/romstage.c
+++ b/src/northbridge/intel/x4x/romstage.c
@@ -34,16 +34,6 @@ void mainboard_romstage_entry(void)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
-	i82801jx_lpc_setup();
-#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
-	i82801gx_lpc_setup();
-#endif
-
-	mb_lpc_setup();
-
-	console_init();
-
 	enable_smbus();
 
 #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index e4a6c215d8..aaaa28aeac 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -373,7 +373,6 @@ enum ddr2_signals {
 
 void x4x_early_init(void);
 void x4x_late_init(int s3resume);
-void mb_lpc_setup(void);
 void mb_get_spd_map(u8 spd_map[4]);
 void mb_pre_raminit_setup(int s3_resume);
 u32 decode_igd_memory_size(u32 gms);