diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 11:16:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:27:00 +0000 |
| commit | 6b2be99eb1961b6fb0bf0723b7ebe5b084ce77fc (patch) | |
| tree | 60e441e3cc7acce26992a827ebf21332a2e2409c /src/northbridge/intel/x4x | |
| parent | 3896576a165968031b624d4800496b2ca1479096 (diff) | |
nb/intel/x4x/hostbridge_regs.h: Clean up registers
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/hostbridge_regs.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h index fea113f691..00b496dca8 100644 --- a/src/northbridge/intel/x4x/hostbridge_regs.h +++ b/src/northbridge/intel/x4x/hostbridge_regs.h @@ -3,12 +3,12 @@ #ifndef __X4X_HOSTBRIDGE_REGS_H__ #define __X4X_HOSTBRIDGE_REGS_H__ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 #define D0EN (1 << 0) #define D1EN (1 << 1) #define IGD0EN (1 << 3) @@ -19,22 +19,22 @@ #define D3F3EN (1 << 9) #define PEG1EN (1 << 13) #define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_GBSM 0xa4 -#define D0F0_BGSM 0xa8 -#define D0F0_TSEG 0xac -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 #endif /* __X4X_HOSTBRIDGE_REGS_H__ */ |