diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-09-29 18:28:23 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-10-13 05:19:03 +0000 |
| commit | f6aa7d94c8ce003383008c366248faebd1f31e9f (patch) | |
| tree | e0093c0bba8f7fa0cf23bafa780fc628a565b0fd /src/northbridge/intel/x4x | |
| parent | 53e41956256bdf52bb5823838c62674e0e838861 (diff) | |
nb/intel/*/gma: Port ACPI opregion to older platforms
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.
It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.
Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index db96facbef..cf3804d50c 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -26,6 +26,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <commonlib/helpers.h> +#include <cbmem.h> #include "drivers/intel/gma/i915_reg.h" #include "chip.h" @@ -33,11 +34,31 @@ #include <drivers/intel/gma/intel_bios.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/opregion.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) +#include <southbridge/intel/i82801jx/nvs.h> +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/nvs.h> +#endif + #define BASE_FREQUENCY 96000 +uintptr_t gma_get_gnvs_aslb(const void *gnvs) +{ + const global_nvs_t *gnvs_ptr = gnvs; + return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); +} + +void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) +{ + global_nvs_t *gnvs_ptr = gnvs; + if (gnvs_ptr) + gnvs_ptr->aslb = aslb; +} + static u8 edid_is_present(u8 *edid, u32 edid_size) { u32 i; @@ -395,6 +416,8 @@ static void gma_func0_init(struct device *dev) } else { pci_dev_init(dev); } + + intel_gma_restore_opregion(); } static void gma_func0_disable(struct device *dev) @@ -439,6 +462,37 @@ static void gma_ssdt(device_t device) drivers_intel_gma_displays_ssdt_generate(gfx); } +static unsigned long +gma_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + igd_opregion_t *opregion = (igd_opregion_t *)current; + global_nvs_t *gnvs; + + if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) + return current; + + current += sizeof(igd_opregion_t); + + /* GNVS has been already set up */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs) { + /* IGD OpRegion Base Address */ + gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); + } else { + printk(BIOS_ERR, "Error: GNVS table not found.\n"); + } + + current = acpi_align_current(current); + return current; +} + +static const char *gma_acpi_name(const struct device *dev) +{ + return "GFX0"; +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -451,6 +505,8 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .ops_pci = &gma_pci_ops, .disable = gma_func0_disable, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { |