diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:11:28 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:36:01 +0000 |
| commit | aba8fb115802df289007ae9df3269d65cfd008c5 (patch) | |
| tree | bcc7d7fd9a8b32f408b1446d158e7520fcc0abce /src/northbridge/intel/x4x | |
| parent | 26a682c9441b4f7312ff9f69d22029841aa245bd (diff) | |
intel/i945,gm45,pineview,x4x: Move stage cache support function
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/stage_cache.c | 29 |
3 files changed, 12 insertions, 32 deletions
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index cc0a97d052..3118b0980e 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -30,8 +30,5 @@ ramstage-y += gma.c ramstage-y += northbridge.c postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index be9c10f001..54295a9cee 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -29,6 +29,7 @@ #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stage_cache.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -134,6 +135,17 @@ void *cbmem_top(void) return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c deleted file mode 100644 index 47f08c1397..0000000000 --- a/src/northbridge/intel/x4x/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} |