diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-07 12:16:56 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-09 15:51:10 +0000 |
| commit | 64f6b71af5443ac4e1126dc5f5202a1bc8657b31 (patch) | |
| tree | a9dd78971edaf050f8a215332755b1a0f55d6cf1 /src/northbridge/intel/x4x | |
| parent | bc0ec507f2183e28c9b45c34c46ce93ca070aed6 (diff) | |
src/northbridge: Fix typo
Change-Id: I00094028036f33892362b935899e1bceef1da625
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 49afdc3b69..1f1c13f092 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -93,7 +93,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) } /* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) |