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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-07-20 23:41:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-30 19:03:27 +0000 |
| commit | 06f818c932be5e19176db0d50939ee89da3267ad (patch) | |
| tree | 9865fb6b53caeb4535b36c0a9375144797c4edc0 /src/northbridge/intel/x4x | |
| parent | e8d0c0092a71c5890a1dfbdc7b941dc5e05b0501 (diff) | |
cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.
This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.
Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x')
0 files changed, 0 insertions, 0 deletions