diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/northbridge/intel/x4x | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 2 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 9cb3df3565..5ccc77e9be 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7e91cc5f5d..8de568a0ea 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -36,9 +36,9 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) #include <southbridge/intel/i82801jx/nvs.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/nvs.h> #endif @@ -71,7 +71,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index ea00f293e1..72ef1a915e 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -25,7 +25,7 @@ #include <halt.h> #include <lib.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ @@ -174,7 +174,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, return CB_ERR; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&decoded_dimm); if (!(decoded_dimm.width & (0x08 | 0x10))) { @@ -383,7 +383,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK) return CB_ERR; - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr3(&decoded_dimm); /* x4 DIMMs are not supported (true for both ddr2 and ddr3) */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index d14809e827..f172623108 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> #else #include <southbridge/intel/i82801jx/i82801jx.h> |