diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-25 20:13:28 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-24 13:03:45 +0000 |
| commit | b5170c3e92b3f0cbce292f3414375b1326f4dd12 (patch) | |
| tree | 8dd7d72aaa67d9727813f70445b667bf526b41a9 /src/northbridge/intel/x4x/x4x.h | |
| parent | f1287266ab7587672080aed2ddbc272a95fba9a3 (diff) | |
nb/intel/x4x: Implement write leveling
DDR3 adapted a fly-by topology which allows for better signal
integrity but at the same time requires additional calibration. This
is done by settings the targeted rank in write leveling mode while
disabling output buffer on the other ranks. After that the DQS signal
gets sampled over DQ until a transition from high to low is found.
Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 53b73ae364..34979a01da 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,6 +373,8 @@ void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); int do_write_training(struct sysinfo *s); int do_read_training(struct sysinfo *s); +void search_write_leveling(struct sysinfo *s); +void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); extern const struct dll_setting default_ddr2_667_ctrl[7]; extern const struct dll_setting default_ddr2_800_ctrl[7]; |