diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-11-30 18:40:38 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-02-17 23:44:06 +0100 |
| commit | 97e13d84c30c308c3b2bc629b38e6bcc9565dc3a (patch) | |
| tree | e177a3c3b2cb9804767d7bbee0cb735ddc001246 /src/northbridge/intel/x4x/x4x.h | |
| parent | 17335fab175ed1a16f61729b03c1fbeeec366f37 (diff) | |
nb/intel/x4x: Fix raminit on reset path
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f5cd..66d765ab83 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -87,8 +87,8 @@ #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 1) -#define PMSTS_BOTH_SELFREFRESH (1 << 0) +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) #define CLKCFG_MCHBAR 0x0c00 #define CLKCFG_FSBCLK_SHIFT 0 @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_WARM_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0, |