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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-25 19:54:49 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-24 13:04:47 +0000 |
| commit | 3fa103a60261a3cd1925858a317dc1ffa89797f7 (patch) | |
| tree | 93aa9beb025765eb75e6351ea65480a530fcac95 /src/northbridge/intel/x4x/x4x.h | |
| parent | b4a78045d572d621ec54bd7c061c4b995a1515a7 (diff) | |
nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 34979a01da..13ca783ac9 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -392,6 +392,9 @@ extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; +extern const u32 ddr3_c2_tab[2][3][6][2]; +extern const u8 ddr3_c2_x264[3][6]; +extern const u16 ddr3_c2_x23c[3][6]; struct acpi_rsdp; #ifndef __SIMPLE_DEVICE__ |