diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-11 17:09:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 07:40:26 +0000 |
| commit | 1848ba3b54dec516471a4a9fce4410ad62918b13 (patch) | |
| tree | 42aa88e95ba2749876d3a0d1e25d56000af6586b /src/northbridge/intel/x4x/x4x.h | |
| parent | 701da39fb7ab9c32e3885c5428b1ee28c6ca5e04 (diff) | |
nb/x4x/raminit: Decode ddr3 dimms
Since this memory controller supports both DDR2 and DDR3 allow it to
decode both while making the dram type mutually exclusive.
Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 5017aa030a..cc17ed6e91 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,6 @@ struct rcven_timings { /* The setup is up to two DIMMs per channel */ struct sysinfo { int boot_path; - int max_ddr2_mhz; enum fsb_clock max_fsb; int dimm_config[2]; |