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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 15:44:27 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:28:52 +0000
commitecec9474d808f532822091c5a6069f57abc1c81d (patch)
treea60107551596d2bdd35c135865a1671c10b143e5 /src/northbridge/intel/x4x/x4x.h
parentf4fa1e1d06b5c68b746274c39f23cc8b05801d90 (diff)
nb/intel/x4x: Change signature of `decode_pciebar`
Rename it and make it return an int, like other northbridges do. Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r--src/northbridge/intel/x4x/x4x.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 133f31d174..bb51c60fd8 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -331,7 +331,7 @@ void mb_pre_raminit_setup(int s3_resume);
u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm);
u32 decode_tseg_size(const u32 esmramc);
-u8 decode_pciebar(u32 *const base, u32 *const len);
+int decode_pcie_bar(u32 *const base, u32 *const len);
void sdram_initialize(int boot_path, const u8 *spd_map);
void do_raminit(struct sysinfo *, int fast_boot);
void rcven(struct sysinfo *s);