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| author | Damien Zammit <damien@zamaudio.com> | 2016-05-21 01:56:01 +1000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-31 20:02:09 +0200 |
| commit | a090ae04c285c4086973e826a36fe87dfeb74d9e (patch) | |
| tree | 94c602c9eb872d9e153705a144f0f30b7b8d8fe7 /src/northbridge/intel/x4x/x4x.h | |
| parent | 2b2f465fcb1afe4960c613b8ca91e868c64592d4 (diff) | |
nb/intel/x4x: Add DMI/EP init
The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code. There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.
Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14925
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e1ef745867..17810aa3cb 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -315,6 +315,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); +void x4x_late_init(void); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); |