nb/intel/x4x: Refactor setting default dll settings

This patch pushes these large default delay tables to a different file
to reduce cluttering up the actual raminit source. While doing so it
also uses more but smaller arrays and also adds the respective default
delays for DDR3 which are not yet used in this patch.

This patch add a function to set the read DQS delays instead of just
programming magic values. (This will prove useful for DQS read
training)

To prepare for adding trainings on the delay values it stores these
default delays in the sysinfo struct to program those. Later when
trainings are implemented those trained values will be used instead of
these safe default values, via using the cached sysinfo in 'mrc'
cache.

TESTED on DG43GT (still works fine)

Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 28 insertions, 16 deletions

diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 70c6525bba..146f865647 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -250,6 +250,11 @@ struct dll_setting {
 	u8 coarse;
 };
 
+struct rt_dqs_setting {
+	u8 tap;
+	u8 pi;
+};
+
 enum n_banks {
 	N_BANKS_4 = 0,
 	N_BANKS_8 = 1,
@@ -303,6 +308,13 @@ struct sysinfo {
 	struct dimminfo	dimms[4];
 	u8		spd_map[4];
 	struct rcven_timings rcven_t[TOTAL_CHANNELS];
+	/*
+	 * The rt_dqs delay register for rank 0 seems to be used
+	 * for all other ranks on the channel, so only save that
+	 */
+	struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][8];
+	struct dll_setting dqs_settings[TOTAL_CHANNELS][8];
+	struct dll_setting dq_settings[TOTAL_CHANNELS][8];
 };
 #define BOOT_PATH_NORMAL	0
 #define BOOT_PATH_WARM_RESET	1
@@ -316,22 +328,6 @@ enum ddr2_signals {
 	CTRL1,
 	CTRL2,
 	CTRL3,
-	DQS1,
-	DQS2,
-	DQS3,
-	DQS4,
-	DQS5,
-	DQS6,
-	DQS7,
-	DQS8,
-	DQ1,
-	DQ2,
-	DQ3,
-	DQ4,
-	DQ5,
-	DQ6,
-	DQ7,
-	DQ8
 };
 
 #ifndef __BOOTBLOCK__
@@ -346,6 +342,22 @@ void rcven(struct sysinfo *s);
 u32 fsb2mhz(u32 speed);
 u32 ddr2mhz(u32 speed);
 
+extern const struct dll_setting default_ddr2_667_ctrl[7];
+extern const struct dll_setting default_ddr2_800_ctrl[7];
+extern const struct dll_setting default_ddr3_800_ctrl[2][7];
+extern const struct dll_setting default_ddr3_1067_ctrl[2][7];
+extern const struct dll_setting default_ddr3_1333_ctrl[2][7];
+extern const struct dll_setting default_ddr2_667_dqs[8];
+extern const struct dll_setting default_ddr2_800_dqs[8];
+extern const struct dll_setting default_ddr3_800_dqs[2][8];
+extern const struct dll_setting default_ddr3_1067_dqs[2][8];
+extern const struct dll_setting default_ddr3_1333_dqs[2][8];
+extern const struct dll_setting default_ddr2_667_dq[8];
+extern const struct dll_setting default_ddr2_800_dq[8];
+extern const struct dll_setting default_ddr3_800_dq[2][8];
+extern const struct dll_setting default_ddr3_1067_dq[2][8];
+extern const struct dll_setting default_ddr3_1333_dq[2][8];
+
 struct acpi_rsdp;
 #ifndef __SIMPLE_DEVICE__
 unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);